Download failed by iMPACT.

[pusik.park]

I connected Platform Cable USB to J7 JTAG header.
My NetFPGA's revision was 3.
After boundary scan's "initialize chain", xc2s200 and xc2vp50 appeared together with connecting each other.
I tried to program the assigned reference_nic.bit obtained by NetFPGA homepage or xxx.bit, which I generated by iMPACT of Xilinx ISE 10.1i WebPack.
However, Program failed.
The message in ISE's output window appeared like

// *** BATCH CMD : Program -p 2
Maximum TCK operating frequency for this device chain: 33000000.
Validating chain...
Boundary-scan chain validated successfully.
'2': Programming device...
PROGRESS_START - Starting Operation.
Match_cycle = NoWait.
Match cycle: NoWait
done.
'2': Reading status register contents...
CRC error : 0
Decryptor security set : 0
DCM locked : 0
DCI matched : 0
legacy input error : 0
status of GTS_CFG_B : 0
status of GWE : 0
status of GHIGH : 0
value of MODE pin M0 : 0
value of MODE pin M1 : 0
value of MODE pin M2 : 0
value of CFG_RDY (INIT_B) : 0
DONEIN input from DONE pin : 0
IDCODE not validated while trying to write FDRI : 0
write FDRI issued before or after decrypt operation: 0
Decryptor keys not used in proper sequence : 0
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 0000 0000 0000 0000 0000 0000 0000 0000
INFO:iMPACT:579 - '2': Completed downloading bit file to device.
Match_cycle = NoWait.
Match cycle: NoWait
INFO:iMPACT - '2': Checking done pin....done.
'2': Programming terminated. DONE did not go high.
PROGRESS_END - End Operation.
Elapsed time = 5 sec.

[gac1]

Hello,

This is a know issue with the current version of the CPCI code. We have fixed this issue and will be releasing an update to the NetFPGA package later this week to early next week.

I'm sorry for the inconvenience. If you need to be able to download using IMPACT before the next release let me know and we may be able to get the the newest CPCI image that will be released.

[RyanWhelan]

Can you explain the fix to this issue? I've been modifying CPCI and I'm encountering this error when using iMPACT to program the FPGAs.

Thanks,
Ryan Whelan

[grg]

Hi Ryan,

Are you having problems reprogramming the Spartan or the Virtex? If you're having trouble reprogramming the Virtex then perhaps your Spartan design is holding the RP_PROG_B signal low?

[RyanWhelan]

Glen,

I was having trouble reprogramming the Virtex. Including the cnet_reprogram module on the Spartan solved this issue.

Thanks,
Ryan