Synthesis poor performance

[Raframos]

Hi,

I tried to synthesize reference_nic design and found some poor results.
Does anybody know if reference_nic meets 125 MHz maximum frequency after synthesis?

Thanks


Timing summary:
---------------

Timing errors: 0 Score: 0

Constraints cover 650401 paths, 24 nets, and 95569 connections

Design statistics:
Minimum period: 10.442ns (Maximum frequency: 95.767MHz)
Maximum path delay from/to any node: 1.990ns
Maximum net delay: 4.900ns
Minimum input required time before clock: 2.865ns
Minimum output required time after clock: 4.689ns


Analysis completed Mon Sep 21 17:56:48 2009
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[jnaous]

You've misread the output. I don't know what the clock frequency refers to here, but all the constraints (including clocks) have been met: Timing errors: 0 Score: 0

So the design will run at the right frequency. The problem is that the tool doesn't know which is your design's real clock.