Timestamp

[Panxter]

Hi to all,

I'm a newbie to NetFPGA and to verilog.
I'm trying to find the timestamping module in Packet Generator. I would like to modify it a bit.
Could please someone help me?

[chaos]

mac_grp_time_stamp.v under projects/packet_generator/src

[Panxter]

Thanks, but isn't it only for the PTP protocol?

As I think, the counter (counter_val) for the timestamp is incremented in stamp_counter.v, then this code does the timestamping in rx_queue.v. :

small_fifo
#(.WIDTH(TIMESTAMP_WIDTH),
.MAX_DEPTH_BITS(7))
pkt_timestamp_fifo
( .din (counter_val[COUNTER_WIDTH-1:COUNTER_MIN_POS]),
.wr_en (rx_pkt_begin),
.rd_en (pkt_timestamp_fifo_rd_en),
.dout (timestamp),
.full (),
.nearly_full (),
.empty (pkt_timestamp_fifo_empty),
.reset (reset),
.clk (clk)
);

Am I right? or totally wrong?

[chaos]

Yes. I think you're right :)

[Panxter]

Wow.

First of all, I would like to modify the code to measure the time between packets.
My idea is : If the timestamping had happened, then clear the counter, to start counting from 0.

Do you have any idea how to do this ? I'm trying to find a signal that could reset the counter.

[chaos]

Not necessary to reset the counter. It's a clock. You just need to calculate the increamental number between two packets.
And the counter width is large enough for a long long period of time.

[Panxter]

Not necessary to reset the counter. It's a clock. You just need to calculate the increamental number between two packets.
And the counter width is large enough for a long long period of time.

It's okay, but for me it's not good. My final goal is to synchronize the counter to an external device. So first of all, I need to do what I've mentioned above.