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Forum: Development

Discussion related to development with the NetFPGA platform. This includes both developing projects/modules that run on the hardware and development of the base system.

  1. Question Sticky Thread Sticky: Frequently asked questions

    This is the thread for development frequently asked questions. The list owners will move postings in here as appropriate. See also other FAQ...

    Started by grg, 04-07-2010 07:18 PM
    • Replies: 3
    • Views: 416
    grg
    04-08-2010 09:20 PM Go to last post

  1. error when write() the port of NETFPGA!

    I follow the program as: /////////////////////////////////////////////////////////////////////////////////////// /* * File: send_receive.c ...

    Started by alpha_09, Today 08:27 AM
    • Replies: 0
    • Views: 5
    alpha_09
    Today 08:27 AM Go to last post

  2. Error while running nf_run_test.pl

    NetFPGA environment: Root dir: /home/pjgy5/netfpga Project name: crypto_nic Project dir: /home/pjgy5/netfpga/projects/crypto_nic...

    Started by pari685, 09-04-2010 06:14 PM
    nf_run_test.pl
    • Replies: 3
    • Views: 39
    pari685
    Today 04:14 AM Go to last post

  3. Unplugging links (port change events)

    Hello. I've got a question about the port change event. For some code I'm developing with OpenFlow, I need the NetFPGA to detect it when a link is...

    Started by ElisaRojas, 08-30-2010 11:11 PM
    change, event, link, plug, port
    • Replies: 0
    • Views: 30
    ElisaRojas
    08-30-2010 11:11 PM Go to last post

  4. Data Control signal

    Hi, how many can be the module headers? In the wiki there are just 3, is it their maximum number? Thanks for answer Regards

    Started by alex_88, 08-27-2010 07:01 PM
    • Replies: 3
    • Views: 72
    amg_isu
    08-29-2010 06:00 PM Go to last post

  5. Driver Questions

    Hello, In the ISR of the driver, the a variable int_mask is edited and in the end written back to the CPCI. When an interrupt occurs, this...

    Started by amg_isu, 08-24-2010 09:51 PM
    • Replies: 0
    • Views: 46
    amg_isu
    08-24-2010 09:51 PM Go to last post

  6. Simulation/Debugging

    Looking at the forums it seems that folks have both ModelSim SE and DE working with NetFPGA. Has anyone been able to simulate with anything else? I...

    Started by WanderingHill, 04-19-2010 09:08 PM
    debugging, simulation
    • Replies: 4
    • Views: 287
    quocdung89
    08-18-2010 12:38 PM Go to last post

  7. I wander about tx_queue, oq_header_parser, length in module header.

    :) I wander about this. one :) In tx_queue.v(line 186), I didn't find condition to set up 'ENABLE_HEADER'. Is it being used? two:) In...

    Started by routinglab, 08-17-2010 04:48 PM
    • Replies: 0
    • Views: 44
    routinglab
    08-17-2010 04:48 PM Go to last post

  8. Problem with changing the netFPGA reference_nic project to use just 2 eth ports

    Hello, I'm currently working on Pattern Matching project and plan to implement the system onto netFPGA. But the problem is the Pattern Matching...

    Started by now_nev, 08-09-2010 09:43 AM
    physdesignrules error, reference nic, unconnected
    • Replies: 3
    • Views: 99
    HaoyuSong
    08-16-2010 08:07 PM Go to last post

  9. question about a module implementation

    I designed a small module which is located between the in_arb and output_port_lookup modules. To test it, I connected nf2c1 and nf2c2 together and...

    Started by HaoyuSong, 07-23-2010 05:34 PM
    2 Pages •
    1 2
    • Replies: 10
    • Views: 274
    HaoyuSong
    08-06-2010 03:48 PM Go to last post

  10. Can't find nf2_top_par.ngd

    I synthesized openflow project. But I am not able to find the nf2_top_par.ngd in the synth folder. What is the problem thanks in advance

    Started by abhilashrs, 07-26-2010 06:17 AM
    • Replies: 6
    • Views: 127
    amg_isu
    07-29-2010 04:26 PM Go to last post

  11. XBD file for netfpga

    :confused: , hi does anyone have the XBD file for netfpga ? if not , then who ever wrote the xbd file for their own board ? i am confused about the...

    Started by jameschen, 07-26-2010 12:42 AM
    xbd file
    • Replies: 2
    • Views: 116
    jameschen
    07-29-2010 03:21 PM Go to last post

  12. Design using ISE

    Hello, I copied all sources of openflow project to ISE environment and provide IP cores as required. I succeeded in making the bit file. But...

    Started by abhilashrs, 07-28-2010 01:24 PM
    • Replies: 0
    • Views: 81
    abhilashrs
    07-28-2010 01:24 PM Go to last post

  13. Coding of syncfifo_2048x72 is

    How syncfifo_2048x72 is coded. Going through the code I doubt that it's not created by core generator. If it is created by core generator...

    Started by abhilashrs, 07-27-2010 01:00 PM
    • Replies: 2
    • Views: 90
    abhilashrs
    07-28-2010 04:42 AM Go to last post

  14. Talking About Clean-Slate Design

    I have the goal of develop in one mounth, a project that involve both software and hardware and i will do it with netFPGA. I adquired a couple of...

    Started by JovannyISOK, 07-01-2010 03:19 PM
    clean-slate, guide user, java
    • Replies: 2
    • Views: 165
    scut_alex
    07-28-2010 03:46 AM Go to last post

  15. Linux drivers

    Hello, In the interrupt service routine in the drive (v. 2.0.0 beta), nf2_disable_irq() is called which seems to disable the interrupts in the...

    Started by amg_isu, 07-23-2010 02:52 AM
    • Replies: 1
    • Views: 98
    divinekumar
    07-23-2010 04:57 PM Go to last post

  16. Embeded Linux

    Hi , :p i am confused to make the Embeded Linux run on the NetFPGA these days. Can Embeded Linux run on the NetFPGA ? Did anyone do this before ?...

    Started by jameschen, 06-29-2010 11:31 AM
    2 Pages •
    1 2
    embeded linux
    • Replies: 10
    • Views: 330
    jameschen
    07-23-2010 04:36 PM Go to last post

  17. Regiter location in Netfpga

    Please tell me about the location of register system in NetFPGA board Whether it is placed in virtex chip or RAM. As I need to develop from...

    Started by abhilashrs, 07-20-2010 09:06 AM
    • Replies: 3
    • Views: 126
    Eastzone
    07-21-2010 01:55 AM Go to last post

  18. Error in synthesis

    I provide all verilog source files to /src and try to synthesis the project. But I got the following error. ...

    Started by abhilashrs, 07-20-2010 09:12 AM
    • Replies: 1
    • Views: 101
    Eastzone
    07-20-2010 03:51 PM Go to last post

  19. Using PCAP file as input to Modelsim

    All, Being able to simulate exactly the same data as is being fed into the hardware is something I have noticed is very useful for debugging. I...

    Started by amg_isu, 07-16-2010 10:23 PM
    • Replies: 0
    • Views: 78
    amg_isu
    07-16-2010 10:23 PM Go to last post

  20. Reference Switch Maximum packet size

    Hi, Is there any upper limit on the maximum packet size supported by the reference_switch design in the new Netfpga2.1 source. The verification...

    Started by janardhan_us, 07-14-2010 03:46 AM
    • Replies: 2
    • Views: 151
    janardhan_us
    07-16-2010 04:35 PM Go to last post
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