NetFPGA-10G Information

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Release Note

We are proud to announce the new 4x10GE version of NetFPGA: The NetFPGA-10G!

Hardware:
The NetFPGA-10G board was designed by the NetFPGA team and is available from HTG. It has 4 x 10GigE SFP+ interfaces, a PCI Express interface to the host (Gen2 x8 channels), and a Xilinx Virtex-5 TX240T FPGA. The board has SRAM and DRAM (27 MBytes QDRII SRAM, 288 MBytes RLDRAM-II) and a high bandwidth expansion connector for daughter-cards. Further technical details on the board, along with purchasing information, can be found at HTG's website here. You can see a photo of the board at NetFPGA.org.

Price:
The Academic price is $1,675.

Code Base:
This first release comes with a modest (but steadily growing) code base of hardware and software to get you started. The design flow is based on EDK and AXI, and all platform documentation can be found at NetFPGA-10G PBWorks site. You can download the code base as a git repository from the NetFPGA-10G GitHub site after you have registered as explained on the Getting Started Guide.

We hope you enjoy the new platform and we look forward to your feedback, comments, and discussion on the mailing list. It is a pleasure and honor to work with the whole NetFPGA community, and we look forward to working with you in 2011. Together, let's develop great new open-source networking hardware! Let's enable great teaching and research in networking hardware! We will update you as we prepare for major new releases of the code base in the coming months. Stay tuned!

Hardware Features

• Xilinx Virtex-5 XC5VTX240TFFG1759 -2
• Four SFP+ interface (using 16 RocketIO GTX transceivers and 4 PHY devices)
• Supports both 10Gbps and 1Gbps modes
• X8 PCI Express Gen 2 (5Gbps/lane)
• Twenty Configurable GTX Serial Transceivers (available through two high-speed Samtec connectors)
• Three x36 QDR II ( CY7C1515JV18)
• Four x32 RLDRAM II ( MT49H16M36HT-25)
• Mictor Connector for debugging
• Two Platform XL Flash (128mb each)
• One Xilinx XC2C256 CPLD
• One DB9 (RS232)
• User LEDs & Push Buttons
• 9.5" x 4.25" board size

Board

FPGA Design

We're planning the following FPGA design releases:

Production test design: (complete) This design allows to test all the interfaces on the board (QDRII, RLDRAMII, 10G interfaces, PCIe, and expansion slot) and is only available in form of bitstream with manual.

First FPGA infrastructure design: (complete) This design will be released as source code and contains mainly the network interfaces (1G and 10G mode), with a simplistic packet generator and checker, as well as a control processor subsystem.

Full FPGA infrastructure release: (in progress) This release comes with reference designs that operate the NetFPGA-10G as a NIC in 1G or 10G mode with all 4 ports active. In addition, the release provides the basic building blocks of all future designs. As such it will feature all memory controllers, and PCIe endpoint with DMA, as well as software.

More information

For more information, visit NetFPGA website for the latest update – http://www.netfpga.org, or if you haven’t already, sign up to netfpga-announce mailing list https://mailman.stanford.edu/mailman/listinfo/netfpga-announce