You are here: Foswiki>NetFPGA/OneGig Web>Contributed (15 Jun 2010, Main.MartinLabrecque)EditAttach

Contributed

This page lists contributions from the NetFPGA developer community. Feel free to add links to your NetFPGA contribution below. In addition to this list of projects developed specfically for the NetFPGA, see also the list of research projects on the researchers page which more generally describe networking projects implemented on FPGAs.

Show Contents...Hide Contents...

Rice University: Network Systems Architecture Class

Owner: Scott Rixner, Jeff Shafer

Description: The NetFPGA system was used at Rice University to teach a class on network systems architecture. It was modeled on Stanford's CS344 course where students construct an IP Router. We learned a lot about NetFPGA that is applicable towards both research and education applications, and wanted to share some of our thoughts with the user group.

Extended Description: Contributed-Rice

Router buffer sizing (University of Toronto)

$Description: In this work, we set up a test-bed of several Dell Power Edge 2950 servers each equipped with NetFPGA boards to perform experimental studies on router buffer sizing. With NetFPGA as the router, one can control the buffer sizes with high precision, based on the number of packets or bytes, and without the worry of hidden buffers in the system. We have also added a module to the NetFPGA-based router to collect accurate buffer occupancy time-series, and to accurately measure the bottleneck link's utilization and loss rate. We have also written scripts to automatically set up a test-bed of NetFPGA routers. The scripts discover the network topology, set up the ARP tables, configure IP addresses, and routing in the test-bed.

Owner: Yashar Ganjali: http://www.cs.toronto.edu/~yganjali/

Project URL: http://www.cs.toronto.edu/~yganjali/research/projects/bsizing/

Click Any-to-Any test (ICSI)

Description: Any to Any test using click, http://www.icsi.berkeley.edu/~nweaver/ntest.tar

Owner: Nicholas Weaver, ICSI

Summary: This test invokes Click to run an "any to any" send test. It first sends a total of 16 ethernet Broadcast packets, with the SRC mac as CA:FE:BA:BE:00:p# and the dest MAC as FF:FF:FF:FF:FF:FF, ethertype 0x890F (an unassigned ethertype). It will then repeat forever, sending a packet from a pseudo-random SRC to a different pseduo-random DST, ethertype 0x890F.

Extended Description: Contributed-Any_to_Any

Deficit Round Robin (DRR)

Description: Deficit Round Robin Module

Owner: Peyman Kazemian & Drew Mazurek

Description: Deficit Round Robin (DRR) is an Algorithm for providing QoS among flows in a router by dividing bandwidth fairly among the flows (Shreedhar, M.; Varghese,G. "Efficient fair queueing using deficit round robin). This contributed project contains a general purpose DRR implementation that can be added to your project by simply inserting the module after the output queues in pipeline. The definition of flow is arbitrary here. Flows are classified by a module that comes before generic DRR module and tag each packet with a number identifying the flow it belongs to. In current distribution, we have a classifier module that classifies packets based on ToS and Input Port. This can be easily changed with whatever criterion desired for packet classification (look at packet classifier module)

URL: DRR-NetFPGA

Princeton: MTU Test Scripts

Jen Rexford, Eric Keller

NetFPGA Cluster at Stanford University

Owner: John W. Lockwood

Description: The NetFPGA cluster consists of two racks of 40 (total) NetFPGA machines. The cluster has managed power, KVM-over-IP consoles, and a fully programmable topology of 160 Gigabit Ethernet ports.

Extended Description: NetFPGA Cluster

Emulab: On-line Testbed

Jay Lepreau, David Johnson, Mike Hibler

PTP: Precision Time Protocol

This project implements PTP standard by using NetFPGA platform. PTP is a simplified version of "IEEE 1588 standard which is a protocol designed for synchronizing real time clocks in the node of a distributed system that communicates using a network" [1]. In this project required changes has been made in NetFPGA's reference_router design in order to support PTP. In this document first we explain briefly how PTP works. In the following the software and hardware parts of the design are explained. For those people which are interested in using PTP router for clock synchronization, a chapter is designated to explain how to setup the nodes and configure the system. Finally some intermediate results are presented which are achieved using the PTP router for synchronization.

People involved in this project are Sara Bolouki, Peter Pawlowski, Jad Naous.

300 px

$ Different parts of the project $1- PTP System? $1- 1588 software? $2- Changes in the router to support 1588 :$2-1 Filtering the input ptp packets :$2-2 Generate a time stamp for valid ptp packets $3- Steps of adding registers :$3-1 Adding registers to existing register block inside nf2_core :$3-2 Adding registers for a new module inside nf2_core $3- Software hardware interface? $4- Experiment results

RCP: Rate Control Protocol

Description

Implement RCP protocol on NETFPGA http://yuba.stanford.edu/rcp/

Owner

Sara Bolouki, Nandita Dukkipati, Jiang Zhu $ Steps :

 1- Change Roueter Verilog code to support RCP 2- Update Driver 3- Implement the software part of RCP 4- Test the system

$ Documents:

 1- user_data_path.vcd

$ Add the registers

Live CD for OpenSuSE

Description: Live CD based on openSuSE 10.3 that has OpenFlow and NetFPGA binaries installed
Owner: Jad Naous
URL: LiveCD

Packet generator

Description: A simple "packet generator/capture" system that uses the NetFPGA to transmit sequences of packets. In this design, the packet sequence is loaded into SRAM and the NetFPGA replays the sequence from SRAM. Sequences can include delays between packets or can simply be replayed at line rate. The design supports separate sequences on each of the 4 ports. The design also supports iterating over the sequences any number of times.
Owner: Glen Gibb
URL: Packet generator wiki page

University of Massachusetts Lowell: Advanced Computer Architecture Class

Description: A graduate level course on advanced topics of computer architecture and network systems at UMass Lowell. Students do course projects using NetFPGA development boards and network processor development boards.
Owner: Yan Luo
URL: Course website

Ericsson Research Nomadic Lab & HIIT: Publish/Subscribe

Description: The "future internet" projects PSIRP and ICT SHOK are evaluating new approaches to internetworking. One of the most promising new ideas is to apply the publish/subscribe paradigm in the internetworking layer, instead of the currently dominant send/receive paradigm used in most networking protocols today.

Publish-subscribe networks have traditionally been overlays on top of IP. However, now that we are studying what would be the gains of applying this paradigm directly on top of link layer or even bare hardware, we need to evaluate the performance of this architecture against the dominant IP architecture. NetFPGA seems like a good tool to do that, as there is the reference IP router implementation, to which we can compare our own pub/sub-based information router.

Owner: Pekka Nikander
URL: PSIRP project page and ICT SHOK Future Internet page

Extended Description: Contributed-zFilter_sprouter

Network Flow Probe

$ Description:

Owner: Martin Zadnik
Projec Page: Projects:NetFlowProbe

Network Flow Monitor

$ Description:

OpenFlow-MPLS switch

Description
In this project we modified standard openflow switch to be able to support MPLS. for doing this, we allowed matching and rewrite action in the flow table on up to two MPLS labels and supported push and pop actions using virtual ports.

Owner

Peyman Kazemian

URL: project page

VLAN-tag-handler

Description: This design adds/modifies/removes VLAN tags to outgoing packets. Operations(add/mod/remove) and VLAN tag values can be configured per port via registers. The forwarding ports for each input port are also programmable.

Owner: Tatsuya Yabe

URL: VLAN-tag-handler

Port aggregator

Description: This is a sample project using Vlan remover/adder and outport_aggregator modules. This project allows you to decouple each NetFPGA input/output queue from a physical NetFPGA MAC port. This project uses Vlan tag values instead of physical port number to identify its 'source port'. It translates each 'destination port' information into the corresponding Vlan tag (specified through registers) and uses only one actual output port for sending out packet

Owner: Tatsuya Yabe

URL: PortAggregator

BORPH

Description: Port of the BORPH operating system kernel for the NetFPGA platform.
Owner: Brandon Hamilton
URL: BORPH wiki page

NetThreads-RE (v2.0) and NetThreads (v1.0)

Description: soft processor on NetFPGA enhanced for high-throughput packet processing so that anyone can program NetFPGA in C with the supplied compiler. NetThreads-RE is geared towards forwarding/routing (and has a number of added features), while NetThreads is for generic packet processing.
Owner: Martin Labrecque
NetThreads-RE URL: latest wiki
NetThreads URL: wiki

My project

$
: Description


Owner: Add a link to My Name
URL: Add a link to the a project website that has details about the work (publications, project description, or Wiki page)

Add your project here

Description: We encourage you to list and link your project here. To edit this page, you must be member of the Beta-Plus program. Once registered, just cut and paste this text block above this line and edit this Wiki page.
Owner: Add a link to My Name
URL: Add a link to the a project website that has details about the work (publications, project description, or Wiki page)