Preparing for the 1G General Release (All)

• Target Date: Mar 2009
• Features
  • Register Interface - XML
    • Projects can overlap register address locations
    • Binaries would map addresses at compile-time
      • Hardware bitfile
        • List of modules loaded with versions
      • Software driver
        • Would need to verify that same modules and versions are loaded
    • Needs to be extensible
      • New projects should be able to add registers
      • New versions of a project should be able to add/remove registers
    • Glen and Jad have discussed specification
      • http://netfpga.org/netfpgawiki/index.php/Register_system_2.0
      • We do not yet have a Schema defined
    • Perl code needs to generate Verilog and C from XML needs be implemented
  • CS-style student could implement this program from a clear specification
  • Configuration Script to verify configuration of lab of machines
  • YUM install is good
  • Use team-city to build packages
  • Regression test update
    • Use the verify test for regression test
    • Make it easier to write verification tests
    • Action/Delay for response mechanism is not clean