ISE setup

1. Start ISE
2. Create a new project. Give the project a name (eg. ethernet_switch) and create the project in a directory called ise inside the project directory (eg. NF2/hw/NF_2.1_cs344_starter/ise)
3. Set the project options appropriately:
   • Faimily: Virtex2P
   • Device: XC2VP50
   • Package: 1152
   • Speed: -7
   • Simulator: ModelSim
   • Preferred Language: Verilog
4. Don't create any source files.
5. Add all of the sources inside src (and any subdirectories in src). Clear the "Copy to project" flag from each source file.
6. Click finish and wait for ISE to import the files.
7. Select nf2_top.v in the source tree.
8. Right-click on the Synthesize process and select properties.
9. Set the "Property display level" to Advanced
10. On the Synthesis options page:
    • Add the project include directory to the Verilog Include Directories
    • Set Keep Hierarchy to Yes
11. Click OK
12. Right-click on nf2_top.v and select Add Source.
13. Add the nf2_top.ucf file from the synth directory (don't add a copy).
14. Right click on nf2_top.v and select Add Copy to Source.
15. Add all of the .xco files from the synth directory.