PHY test

Individual PHY Test

Use an address swap module to simply swap source and destination addresses of any incoming packet and send it out again. This will allow testing of a single PHY. This test is provided as an example design by coregen when the TEMAC core is generated. Check the results using ethereal/tcpdump.

Forwarding Test

Simply forward any packet coming in on port 1 out of port 2, and vice-versa, and any packets coming in on port 3 out of port 4 and vice-versa. Again, check results on ethereal.

Self-test

Connect an ethernet cable between ports 1 and 2, and between ports 3 and 4. Generate packets inside the FPGA, and send packets out through one port and echo it back at the receiving port. This test will be integrated with Glen's self-test code to light an LED if the packets received are as expected.

Algorithm

Packet data types:

0 = 0x0000...

1 = 0xffff...

2 = 0x5555...

3 = 0xaaaa...

Packet sizes = 60, 799, 1500, 1400 //last value to be changed to 2000 once jumbo frames are enabled
Ports = 0, 1, 2, 3

For each packet type, t
   For each size, s
      For each Port, p
         Send packet out of port p, and wait for packet from complementary port
         If packet does not arrive within 16000ns
            Flag error and continue
         For each word in Rx packet
            if rx word != tx word
               flag error
         if status word != 0
            flag error
         If Rx pkt length != Tx pkt length
            flag error

Error logging

Errors are logged into a register block. The registers record the following information

• Error count (up to 2^16)
• For each error (up to the first 16 errors)
  1. Error code (list of values and their descriptions is given below)
  2. The packet type
  3. The packet size
  4. The Rx Port
  5. Expected value
  6. Seen Value

The packet, type and port can be used in combination to determine which test iteration failed. To determine the sort of failure, we can use the error code, expected value and seen value fields in the following way:

Within the phy-test register module, the addresses allocated to each of the blocks are as follows:

Simulation

In order to verify that the self test code works, the following conditions were simulated

1. All TX packets received from the system are copied back into the complementary ingress port. This is the test with no injected failures. The error count should return 0 at the end of the test
2. One RX packet is sent that is 1 byte shorter than the corresponding TX packet. There should be a length mismatch
3. One RX packet is sent back with a single bit different from the TX packet. There should be a data mismatch
4. One packet was simply not echoed back to the system. This was to ensure that the timeout mechanism worked as it should. The system should raise a timeout error, and continue to transmit the next packet in the test sequence.
5. A packet was transmitted where every byte of the data had one bit off. This was to ensure that errors in back-to-back bytes/words were recorded correctly.

All tests passed the simulation.