Task list

Show Contents...Hide Contents...

Contents

• New boards
• Self test
• General hardware
• GUI
• Reference router hardware
• Tutorial
• General software
• Public Release Issues
• Old task list
• To do
• Fixes to Reference Router v2

New boards

Task	Priority	Deadline	ETA	Assigned To	Proposer
Re-run selftest on new boards (batch 1)	High				Glen
Perform Virtex reprogramming stress test to identify power supply issues	High				Glen
Spartan reprogram from Virtex test	Done		6/22/07	Glen	Glen
Run selftest on new boards (batch 2)	Done				Glen

Self test

Task	Priority	Deadline	ETA	Assigned To	Proposer
DMA interface test	Normal			Jianying	Glen
Produce new self test for Digilent	Normal				Glen
Clock select test	Done		6/19/07	Glen	Glen

General hardware

Task	Priority	Deadline	ETA	Assigned To	Proposer
Minimal Spartan design to support reprogramming	Normal				Glen
Clean up Virtex -> Spartan reprogramming design	Done			Glen	Glen
Virtex design to reprogram Spartan	Done		6/22/07	Glen	Glen

GUI

Task	Priority	Deadline	ETA	Assigned To	Proposer
Fix negative queue occupancies and negative numbers in statistics	High				Jad
Fix Event capture GUI to be updated from hardware	High				Jad
Fix details panel to disallow multiple instances of the same window	Normal				Jad
Integrate with management interface	Normal				Jad
Enhance details panel to provide quick feedback about current state of all modules (eg. enabled/disabled/rate)	Normal				Glen
Add read-only mode to GUI to prevent changes during demonstrations	Normal				Glen
Add save/load state to more modules (not just IP/routing/ARP tables)	Normal				Glen
Improve error handling when loading a config file with erroneous entries	Normal				Glen
Add support to read configuration from the hardware and dynamically setup available modules	Low				Jad
Fix the event capture to use sockets instead of jpcap	Low				Jad

Reference router hardware

Task	Priority	Deadline	ETA	Assigned To	Proposer
Add hit counter for ARP entries so that the software knows not to time them out	High				Jad
Change all counters to saturating and self-clearing after a read	High				Jad
Rewrite small async fifo -- currently uses third part code	High				Glen
Work out the set of registers we want for the CPU queues (they currently have NONE!)	Normal				Glen
Add packet length header to packets coming in from Rx queues	Normal			Glen	Jad
Simplify output queues registers/counters and modules by using the length header	Normal				Jad
Implement larger Routing table and ARP cache not using cams	Normal				Jad
Add a Host queue so that it looks like an additional port - depends on DMA implementation	Normal				Jad
Restructure/rewrite the modules to optimize area	Normal				Jad
Remove unnecessary registers	Normal				Jad
Make sure to register all outputs (inputs can be registered as needed)	Normal				Jad
Remove unnecessary pipeline registers	Normal				Jad
Solve race conditions for reads and writes to tables	Normal				Jad
Add per module registers to indicate which modules are available/version info	Normal				Jad
Modify the SRAM arbiter to use a more efficient protocol (no wasted cycles)	Normal				Jad
Add code to store_pkt/remove_pkt to verify lengths in simulation	Normal				Glen
Check if the Rx/Tx queues can be modified to use a simpler/more efficient time-domain crossing	Low				Jad
Fix the CPU register queue interface to make it easier (maybe two data words instead of one, and a length)	Low				Jad
Move as many registers into BRAM as possible/maybe centralized counters	Low				Jad
Auto-generate reg_defines.h and NF21RouterLib.pm constants from NF_2.1_defines	Low				Glen
Look at the way broadcast addresses are handled in input packets

(Consider looking at the broadcast bit only)|

Low				Glen
Add general registers: version, project id, ...	Done			Glen	Jad
Put SRAM flops back in SRAM module while maintaining IOB flops	Done			Glen	Glen
Make register access in the user datapath modular, maybe as a packet. Need flush/clear ability	Done			Glen	Jad
Only write one module header into SRAM in the output queues instead of all module headers	Done			Glen	Jad

Tutorial

Task	Priority	Deadline	ETA	Assigned To	Proposer
Using DMA for event capture	High				Jad
Tweaks to the GUI: add read-only mode, fix negative queue occupancies and negative numbers	High				Jad
SR implementation to support multiple hosts on the same link	High				Jad
Tweaks to Event capture: allow pkt queue occupancy correction to fix negative numbers	High				Jad
Simple centralized management interface for all machines to detect misconfigurations/change topologies....	Normal				Jad
Figure out a topology for testing event capture where all hosts can participate	Normal				Jad
HW tweaks: change incrementing statistics registers to saturating and self-resetting after reads	Normal				Jad
Add virtual interface to eliminate need for additional NIC	Low				Nick

General software

Task	Priority	Deadline	ETA	Assigned To	Proposer
Add ability to create/destroy network interfaces on the fly from driver with ioctl	Normal				Glen
Provide batch read/write operations in a single ioctl	Normal				Glen
Add character mode interface in driver with ability to dynamically create/destroy with ioctl	Low				Glen

Public Release Issues

Task	Priority	Deadline	ETA	Assigned To	Proposer
Modify the Simulation Environment to support DMA easily	Normal				Jad

Old task list

Format:

• Write a tasklist -- Mr Manager (Due: 3/1/1981)
• Buy a computer -- Mr Manager (Due: 1/1/1981, Done: 1/2/1981)

To do

• NetFPGA Documentation? -- All
  • What needs to be done for the documentation?
• Simulation Environment
  • Decide on simulation environment -- (Done: 1/22/07)
  • Set up basic simulation environment for CNET/UNET designs -- Glen?
• Base design? -- All
• Simplifying Module interfaces
  • (done) - Implement and test rx_queue
  • (done) - Implement cpu_dma_input_queue
  • (done) - Implement round robin input_arbiter
  • (unnecessary) - Implement user_filter_i
  • (done) - Implement and test switch output_port_lookup
    • (done) - Implement ethernet_parser (simple state machine)
    • (done) - Implement mac_lut using CAM (Xilinx tools generates CAM, need to add LUT, make easy to change for router implementation)
    • (done) - Implement forwarding state machine (connect everything)
    • (done) - Testing
  • (done) - Implement and test router output_port_lookup
    • (done) - Reuse ethernet_parser
    • (done) - Implement ip_parser
    • (done) - Implement lpm_lut using CAM (reuse mac_lut design)
    • (done) - Implement arp_lut using CAM
    • (done) - Implement forwarding state machine
    • (done) - Testing
  • (done) - Implement and test output_queues_arbiter
  • (done) - Implement output_port_demux
  • (done) - Implement and test tx_queue
  • (done) - Implement cpu_dma_output_queue
  • (done) Full system simulations

Fixes to Reference Router v2

• Restructure/rewrite the modules to optimize area
• Remove unnecessary registers
• Make sure to register all outputs (inputs can be registered as needed)
• Remove unnecessary pipeline registers
• Add packet length header to packets coming in from Rx queues
• Simplify output queues registers/counters and modules by using the length header
• (tentative) Move as many registers into BRAM as possible
• Only write one module header into SRAM in the output queues instead of module headers
• Fix the CPU register queue interface to make it easier (maybe two data words instead of one, and a length)
• Packets destined to the CPU should go into the source queue instead of the destination queue (needed so that PWOSPF knows which port a packet came from)
• Check if the Rx/Tx queues can be modified to use a simpler/more efficient time-domain crossing
• Modify the SRAM arbiter to use a more efficient protocol (no wasted cycles)
• Implement larger Routing table and ARP cache
• Add general registers: version, project id, ...
• Solve race conditions for reads and writes to tables
• Make register access in the user datapath modular
• Add hit counter for ARP entries so that the software knows not to time them out

---

Dev