From NetFPGAWiki
- 3- Steps of adding resgisters
- In this project, we needed to add registers for passing the time stamp values to the software and also controlling the counter via the software.
- 3-1 Adding registers to existing register block inside nf2_mac_grp.v
- Inorder to add registers for a module which is instantiated in nf2_core.v and already has register interface these steps should be followed:
- Open /lib/verilog/common/src21/NF_2.1_defines.v file
- Find the module which you want to add resgiters to, in this case (nf2_mac_grp.v) search for MAC_GRP_REG_ADDR_WIDTH
- Add the new resgiters in the Internal Addresses followed by the previous existing registers. These are the registers which were added to the existing nf2_mac_grp.v registers to read the time stamps for each mac.
`define CLK_SYN_COUNTER_RESET `MAC_GRP_REG_ADDR_WIDTH'hd
`define CLK_SYN_TX_LO `MAC_GRP_REG_ADDR_WIDTH'he
`define CLK_SYN_TX_HI `MAC_GRP_REG_ADDR_WIDTH'hf
`define CLK_SYN_TX_VALID `MAC_GRP_REG_ADDR_WIDTH'h10
`define CLK_SYN_RX_LO `MAC_GRP_REG_ADDR_WIDTH'h11
`define CLK_SYN_RX_HI `MAC_GRP_REG_ADDR_WIDTH'h12
`define CLK_SYN_RX_VALID `MAC_GRP_REG_ADDR_WIDTH'h13
- Add the corresponding External Address for each mac. External address for the firt mac is shown in bellow:
`define CLK_SYN_0_COUNTER_RESET({`CORE_BLOCK_1, `MAC_GRP_0_BLOCK_ADDR, CLK_SYN_COUNTER_RESET})
`define CLK_SYN_0_TX_LO ({`CORE_BLOCK_1, `MAC_GRP_0_BLOCK_ADDR, `CLK_SYN_TX_LO})
`define CLK_SYN_0_TX_HI ({`CORE_BLOCK_1, `MAC_GRP_0_BLOCK_ADDR, `CLK_SYN_TX_HI})
`define CLK_SYN_0_TX_VALID ({`CORE_BLOCK_1, `MAC_GRP_0_BLOCK_ADDR, `CLK_SYN_TX_VALID})
`define CLK_SYN_0_RX_LO ({`CORE_BLOCK_1, `MAC_GRP_0_BLOCK_ADDR, `CLK_SYN_RX_LO})
`define CLK_SYN_0_RX_HI ({`CORE_BLOCK_1, `MAC_GRP_0_BLOCK_ADDR, `CLK_SYN_RX_HI})
`define CLK_SYN_0_RX_VALID ({`CORE_BLOCK_1, `MAC_GRP_0_BLOCK_ADDR, `CLK_SYN_RX_VALID})
- The final step is to print out the add the part which prints out the registers
$fwrite(c_reg_defines_fd, "#define CLK_SYN_0_COUNTER_RESET 0x%07x\n", `CLK_SYN_0_COUNTER_RESET<<2);
$fwrite(c_reg_defines_fd, "#define CLK_SYN_0_TX_LO 0x%07x\n", `CLK_SYN_0_TX_LO<<2) ;
$fwrite(c_reg_defines_fd, "#define CLK_SYN_0_TX_HI 0x%07x\n", `CLK_SYN_0_TX_HI<<2);
$fwrite(c_reg_defines_fd, "#define CLK_SYN_0_TX_VALID 0x%07x\n", `CLK_SYN_0_TX_VALID<<2);
$fwrite(c_reg_defines_fd, "#define CLK_SYN_0_RX_LO 0x%07x\n", `CLK_SYN_0_RX_LO<<2);
$fwrite(c_reg_defines_fd, "#define CLK_SYN_0_RX_HI 0x%07x\n", `CLK_SYN_0_RX_HI<<2);
$fwrite(c_reg_defines_fd, "#define CLK_SYN_0_RX_VALID 0x%07x\n", `CLK_SYN_0_RX_VALID<<2);
- 3-2 Adding registers for a new module inside nf2_mac_grp.v
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