DDR2 Block Data Read Write

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Contents 1 Overview 2 Block Level Diagram 3 Interface Signals 4 Waveform

Overview

This module provides a NetFPGA developer the block-of-data read/write interface to the 64MB DDR2 DRAM chips on the NetFPGA card. It has the following salient features:

• The block-of-data read/write signals from and to the user logic accessing the DRAM are all synchronous to the user logic clock. The user logic is insulated from the DDR2 clock domain signals.
• The user logic can request read and/or write of a block of data to the DDR2 DRAM. The read/write requests are arbitrated and granted by a round-robin arbiter. The granted request can then transfer the block of data into/out of the DRAM. No new read/write request will be granted until the outstanding block of data transfer has been completed.
• DRAM operation (including DRAM refresh) details are invisible to the user logic.
• The data width for the user logic is 144 bits. The data width for DDR2 is 64 bits. The user logic clock frequency is 125 M Hz. The DDR2 clock frequency is 200 M Hz.
• To achieve a combined throughput for read and write greater than 9 Gbps, the block size for the user logic to read/write DDDR2 DRAM is 2034 bytes.

Block Level Diagram

• The first diagram shows how the DDR2 block of data read/write interface is used by the user logic to access the DDR2 DRAM.

• The second diagram shows the composition of the DDR2 block of data read/write interface module.

Interface Signals

• The user logic interfaces the following write signals with the DDR2 block-of-data read/write module.

Note: parameter PKT_MEM_PTR_WIDTH = 22 (DDR2 data bus width is 8 bytes. Only burst length of 2 is supported. So there are 4M pieces of 8*2 bytes in the 64MB DRAM), parameter PKT_DATA_WIDTH = 144 (data bus width visible to the user logic) in the design.

Signal Group	Signal Name	Direction	Bits	Description
Request Negotiation	p_wr_req	from user logic to block-of-data rd/wr module	1	1=request for write transfer (data are from user logic to DRAM), 0=otherwise
Request Negotiation	p_wr_ptr	from user logic to block-of-data rd/wr module	PKT_MEM_PTR_WIDTH	the start address of DRAM for transfer. Each unit is 16-byte piece
Request Negotiation	p_wr_ack	from block-of-data rd/wr module to user logic	1	1=the arbiter acknowledges that the write requester can proceed, 0=otherwise
Data Transfer	p_wr_data_vld	from user logic to block-of-data rd/wr module	1	1=the write data is valid, 0=otherwise
Data Transfer	p_wr_data	from user logic to block-of-data rd/wr module	PKT_DATA_WIDTH	the data transferred from user logic to DRAM
Data Transfer	p_wr_full	from block-of-data rd/wr module to user logic	1	1=notify the user logic to pause transfer the next clock cycle until this signal is deasserted, 0=otherwise
Data Transfer	p_wr_done	from block-of-data rd/wr module to user logic	1	1=this is the last write and no more write will be accepted for this block-of-data, 0=otherwise

• The user logic interfaces the following read signals with the DDR2 block of data read/write module.

Note: parameter PKT_MEM_PTR_WIDTH = 22 (DDR2 data bus width is 8 bytes. Only burst length of 2 is supported. So there are 4M pieces of 8*2 bytes in the 64MB DRAM), parameter PKT_DATA_WIDTH = 144 (data bus width visible to the user logic) in the design.

Signal Group	Signal Name	Direction	Bits	Description
Request Negotiation	p_rd_req	from user logic to block-of-data rd/wr module	1	1=request for read transfer (data are from DRAM to user logic), 0=otherwise
Request Negotiation	p_rd_ptr	from user logic to block-of-data rd/wr module	PKT_MEM_PTR_WIDTH	the start address of DRAM for transfer. Each unit is 16-byte piece
Request Negotiation	p_rd_ack	from block-of-data rd/wr module to user logic	1	1=the arbiter acknowledges that the read requester can proceed, 0=otherwise
Data Transfer	p_rd_rdy	from block-of-data rd/wr module to user logic	1	1=block-of-data rd/wr module has data for user logic to read, 0=otherwise
Data Transfer	p_rd_en	from user logic to block-of-data rd/wr module	1	1=user logic reads out one word of data from the block-of-data rd/wr module, 0=otherwise
Data Transfer	p_rd_data	from block-of-data rd/wr module to user logic	PKT_DATA_WIDTH	data transferred from block-of-data rd/wr module to user logic
Data Transfer	p_rd_done	from block-of-data rd/wr module to user logic	1	1=this is the last read data and no more data will be read for this block-of-data, 0=otherwise

Waveform

• Block-of-data Write Transaction Timing Diagram

• Block-of-data Read Transaction Timing Diagram