From NetFPGAWiki

Update on DDR2 (Jianying)

• Jianying- please revised and update the text below
• As of last week - DDR2 memory is working
  • Asynchronous FIFO generated from Xilinx core
    • Read and write interfaces different
    • Empty interface on read interface operates differently in hardware than in simulation when the width of the datapaths were different
    • Work-around: Use the same width for both read and write interfaces, then the inconsistency between the simulation and hardware goes away.
    • Data Rate for aggregated read and write > 9 Gbps
      • Raw DDR2 runs at 200 MHz * 64 bits wide = 12.8 Gbps
      • Using 2034-byte block-size transfers
        • user logic: 1808 bytes of data + 226 byte of control word = 2034 bytes of data
        • DDR2: 14 bytes padding + 2034 bytes for user logic = 2048 bytes = 2KB DRAM block
        • 256 DDR2 clock cycles * 5ns / 8ns = 160 system clock cycles to read/write a block
      • Data size in DRAM = 2048 bytes
      • internal control byte (the extra, 9th byte per 8 bytes of packet data) is packed into the byte streams.
      • 15.0% cycles lost for arbitration and DDR2 access RAS and CAS latency
      • 2.6% cycles lost for DRAM refresh
      • Combining arbitration, DDR2 access latency and DRAM refresh, 17.6% cycles are lost, yielding a utilizable (100% - 17.6%) * 200 * 64 = 10540 M bps throughput to transfer data from/to DDR2 DRAM (half duplex). So 10.54 Gbps / 9 * 8 = 9.36 Gbps packet data throughput excluding the internal control byte is provided by the DDR2 block-of-data read/write module to the user logic in the system clock domain.
    • Documentation
      • http://netfpga.org/netfpgawiki/index.php/DDR2_Block_Data_Read_Write
      • waveform diagrams has been updated in the wiki page
• Make the DRAM code available to other users
  • User1: Martin Labrecque (Toronto)
    • Wants DDR DRAM Controller
    • Would appreciate CORGEN settings and constraints
    • Jianying attached .UCF file (should be included in package)
    • Must be a packaged as a NGC because we can't release the Xilinx code
  • User2: Pankaj Sharma
    • Now has accounts on nf-test machine. (login=pankajs: uid=56620)
    • Jianying has checked the code into the tree
    • Check out as: svn co svn+ssh://nity.stanford.edu/hpn/home/svn/nf2/NF2/new_tree NF2
      • Enter password 3 times
    • cd NF2/lib/verilog/ddr2_blk_rdwr/src/
    • top module: ddr2_blk_rdwr.v
• Instantiated Chipscope embedded in bitfile
  • Ran Chipscope GUI to view signals

Using the DDR2 Memory (Pankaj)

• Progress with DRAM FIFO for packet pipeline
  • Interchange with BlockRAM or SRAM Output Queues
  • include.txt : specify library module for output queue
    • output queue code in nf2/lib/verilog/output_queues/src/{ BRAM, SRAM, }