Dev-HW Interface
From NetFPGAWiki
Contents |
Basic Goal
- Injecting Data from external device onto NetFPGA. After Digital Signal Processing (DSP) , put them into Output Queues in the form of Ethernet Frame (A new Rx Queue)
- 4 main steps: External Interface, DSP, Packetizing, Controlling
Progress by 2008-12-2
- REG interface : MAC/IP/UDP configuration
- SRAM interface : load real-time IQ signals
- Simulator : read data from SRAM and feed it into packet generator
- Testcases : Load data through SRAM, enable the simulator and observe packet out of MAC0 port
Action Items
- Build HW testbed - signal generator, SDR-IQ, NetFPGA, Host PC
- Testcases - Spectrum analysis and comparision
- Investigating DSP on NetFPGA (Xilinx Chip) - Mixer, NGO, LPF, etc
Project Summary
People
Alex Tudor, James Hongyi Zeng
Status
Phase 1: Packet Generator
Packet Style (following Ethernet, IPv4, UDP packet headers)
| CTRL | + | Bits 0–7 | 8–15 | 16–23 | 24–31 | 32–39 | 40–47 | 48–55 | 56–63 | ||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0xFF | 0 | port_dst 16 (all zero) | word_length 16 | port_src 16 | byte_length 16 | ||||||||||||||||||||||||||||
| 0x00 | 64 | mac_dst 48 | mac_src_hi 16 | ||||||||||||||||||||||||||||||
| 0x00 | 128 | mac_src_lo 32 | mac_ethertype 16 | ip_version 4 | ip_header_length 4 | ip_ToS 8 | |||||||||||||||||||||||||||
| 0x00 | 192 | ip_total_length 16 | ip_id 16 | ip_flags 3 + ip_flag_offset 13 | ip_ttl 8 | ip_prot 8 | |||||||||||||||||||||||||||
| 0x00 | 256 | ip_header_checksum 16 | ip_src 32 | ip_dst_hi 16 | |||||||||||||||||||||||||||||
| 0x00 | 320 | ip_dst_lo 16 | udp_src 16 | udp_dst 16 | udp_length 16 | ||||||||||||||||||||||||||||
| 0x00 | 384 | udp_checksum 16 | RESERVED 16 | sequence_num 32 | |||||||||||||||||||||||||||||
| 0x00 | 448 | DSP result 32 | DSP result 32 | ||||||||||||||||||||||||||||||
| 0x00 | 512 | DSP result 32 | DSP result 32 | ||||||||||||||||||||||||||||||
| 0x00 | ... | ... | |||||||||||||||||||||||||||||||
| 0x01 | - | DSP result 32 | DSP result 32 | ||||||||||||||||||||||||||||||
Features
- 32 bit DSP results
- Void Ethernet header
- A UDP header (8 bytes) - Source Port, Dest. Port, Length
- Sequence Number that increments with each packet sent
- Additional details to be determined
- I^2C control
- AGC settings
- LO
Developing Plan (tentative)
Phase 1: Packetizing
- Generate I/Q numbers on NetFPGA natively.
- Load them into FIFO2 waiting to be packetized.
- Packetize them into an IP packet when there are enough elements in the queue.
- Send the packet out through Gigabit Ethernet interface.
Phase 2: DSP on NetFPGA
- Generate numbers simulation
- Two DSP paths: Sin/Cos multiplication, LPF, Decimation, path merger.
- Put the result into FIFO2
- Phase 1 and Phase 2 Joint Test
Phase 3: Hardware interface
- Hardware configuration: 34pin+10pin(Spartan/Virtex connections) read/write
- Synchronization issue: load every number ARC produces correctly into FIFO1
- Load numbers from FIFO1 to DSP input
- Phase 1, 2, 3 Joint Test
Phase 4: Controller
- Remove previously hard-coded parameters: packet size, destination IP address, control parameters, etc.
- Controller - Controls parameters: ON/OFF, Operation Frequency, AGC(Auto Gain Control)
- NetFPGA Controller - Controls NetFPGA's parameters: Demodulation Frequency, Packet Size, Destination IP Address, other IP packet parameters.
- With a GUI if neccessary.
- Phase 1-4 Joint Test
