DevMeeting-2008 10 01

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Agenda for NetFPGA Developers Wednesday, Oct. 1, 2008, 9:30am

Major Agenda Topics

Contents

Role Call 

* [x] Glen
* [x] Jad
* [x] Adam
* [x] Brandon 
* [x] David  
* [ ] Jianying
* [ ] Paul
* [ ] Alex
* [-] Nick (15 minutes late)
* [x] John
* [x] Zeng Hongyi (James)

What are we building to build a community

  • Top priority - Build the NetFPGA user base
  • Means to this end (below)

Application Project Announcements (John)

Announcing Other Projects (All)

  • NIC
  • Reference IPv4 Router
  • OpenFlow Router (Jad)
    • Who is using the LiveCD
    • How are they using the LiveCD
    • What have they asked for
      • Source code
      • Module package for release

VMWare Example

Web Graphics

  • Icon + one-liner (scrolling on main page)
  • Icon + Short summary (on Blog)
  • Icon + Summary + Details (on Wiki)
  • Summary + Regression tests + Code (in Downloadable package)


Developers Workshop

  • Host a SIGCOMM 2009 workshop in Barcelona?
  • HotI tutorial/workshop at Stanford
    • Preference would be to have it local
    • Could be at the end of summer camp
    • Date: Summer 2009
    • Demo session
    • Machines would be setup
  • Design contest-
    • Best implementation for LPM
    • Prize for the best design
      • Scholarship to attend and present at the developers conference

Google Calendar for NetFPGA Meeting (All)

Status of boards at Stanford (Adam)

  • New table: Application/Person -> Boards
Application machines Number Boards Users
I2 Dell 2950 2
nf-test nf-test 12 3-Masa, 1 David, 1 Teamcity
nf-cluster nf-cluster 38 8 used for POMI Class
CS344 (Keith) 5 Better to have machines in lab. Allows students to change topology. These are non-reworked ver 2 boards
Unused non-reworked 2 Need to have the DC/DC converter rewired.
Need Reworked/Fixed 4 Need to be reworked and resoldered.
  • We could send (6+2+4=12 cards to AlphaEMS for rework)

New batch of NetFPGAs

  • Status on 9/29/08
    • 10 cards back-ordered
  • As per call to Jim O'Dell - 9/23/08 (John)
  • Remainder of (500-2-3 = 495 cards / 1000)
    • Assembly: 10/27/08
    • Delivery: 11/01/08
  • Return of first two boards (Adam)
  • Return broken cards directly to Jim (Adam)
    • Return card with bad DRAM clock (label as such)
    • Also return initial two non-working cards (label as such)

Upcoming Tutorials

South Korea

  • Host: KAIST: Sue Moon
    • Glen has offered to go
  • Tentative Date: Feb 23-27, 2009
  • Equipment status: Ordering
  • How can we automate test for tutorial setup?
  • Deadlines for lab setup: _________
  • Advertise with XUP

Toronto (Yashar, Jad)

  • Host: Yashar
  • Setup: Jad - No
  • Tentative Date: Dec. 2008
  • Equipment status: Has Lab ready
  • Could he teach this on his own?

Upcoming Publications/Presentations

Traffic Generator (Adam)

  • Target for FCCM 2008
  • Alex would like a copy for Agilent

OpenFlow (Jad)

Preparing for a General Release

  • We should think about a general release of the NetFPGA code
  • Target Date: Mar 2009 - (was Dec 2008)
  • Features?
    • Register Interface - XML
      • Projects can overlap register address locations
      • Binaries would map addresses at compile-time
        • Hardware bitfile
          • List of modules loaded with versions
        • Software driver
          • Would need to verify that same modules and versions are loaded
      • Needs to be extensible
        • New projects should be able to add registers
        • New versions of a project should be able to add/remove registers
      • Glen and Jad have discussed specification
      • Perl code needs to generate Verilog and C from XML needs be implemented
    • CS-style student could implement this program from a clear specification
    • Configuration Script to verify configuration of lab of machines
    • YUM install is good
    • Use team-city to build packages
    • Regression test update
      • Use the verify test for regression test
      • Make it easier to write verification tests
      • Action/Delay for response mechanism is not clean

Update on Internet2 Deployments

  • Brandon - please update this text
    • Chris Small: IP addresses for connectivity within POP to New York
      • Couldn't log into the machine
      • Public interface eth0 wasn't on-line
    • John Graham
      • Core Directors between Pops
    • which machines are working
    • which machines still need to be installed
    • what is currently being done

Update on DDR2 (Jianying)

  • Instantiated Chipscope embedded in bitfile
    • Ran Chipscope GUI to view signals
  • hpn1 was not reachable yesterday (Tuesday, Sept. 30)
    • Will fix today
  • Next steps: Remotely debug block read & write transfer logic

Survey Results

  1. We can improve our documentation. Some aspects of the project still have sparse coverage, particularly our coverage of DMA (which is complex).
  2. We need to improve error messages in regressions and installation.
  3. We need to make it easier to install the NetFPGA in a host computer. The first Beta release (Beta 1.0) required that users download multiple tarball files and manually install the software. On some systems (depending on how the operating system was installed), dependent files were missing. Users noted that the installation process improved with the Beta 1.2 release that used the yum package manager. CentOS users appreciated having the package manager automatically take care of downloading dependent packages while Ubuntu users complained that we didn’t officially support their Linux distribution.
  4. It should be easier to use the 3rd party tools. Although we give away all of the code for the NetFPGA with a non-restrictive BSD-style license, the users still need to install commercial tools to synthesize and simulate the hardware. The vendors of these tools (Xilinx and ModelSim) make them available at no cost to most universities, but some users still had trouble finding the person at their own institution that had license keys.
  5. Many users want PCIe (PCI-express), and several asked for 10Gb/s Ethernet interfaces.
  6. Some users want a larger FPGA. Although the Virtex2-Pro-50 is a relatively large FPGA, there are newer devices like the Virtex-5 that provide more logic gates. Some users asked for a larger device to implement more complex circuits.
  7. It can take a long time to synthesize new hardware (about 30 minutes to synthesize the reference router).

Provide feedback to those that responded

  • Reward the users for takin the time to complete the survey
  • Let them know that we listened to thier comments
  • Let them know that we awarded a prize to a user
  • Let them know that we are working on these issues and will have more surveys and prizes

Welcome to new potential members

  • Hongyi (James) Zeng: hyzeng@stanford.edu
  • Christine: cavaness@stanford.edu
  • David Underhill

10G 4-port Card (Paul)

  • Update on progress for meeting with Ivo (add text here)
  • Not present to discuss at meeting

Public web viewable Wiki pages

  • The guide pages are now viewable on the public web
  • Configuration file lists public pages
  • LocalSettings.php in /var/www/netfpgawiki

Other possible meeting times

  • 10am on Wednesday (30 minutes later)?
    • Better traffic, More sleep
  • 9am on Wednesday (30 minutes earlier)?
    • Better for Jianying
  • 11am on Wednesday (1.5 hours later)?
    • Conflict for James
  • 11am on Tuesdays (1 day earlier)?
    • Other meetings in afternoon

Additional Topics to Discuss

  • Add items here as needed
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