DevMeeting-2008 10 22

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Agenda for NetFPGA Developers Meeting

  • Wednesday, Oct. 22, 2008, 8:30am (Still at the new time!)

Major Agenda Topics

Contents

Role Call 

[x]=present, [ ]=MIA
(%)= Attendance over previous two weeks (10/8 and 10/15)
* [x] John : (100%)
* [ ] Glen : (100%) (OpenFlow Demo recovery)
* [x] Jad : (90%) (OpenFlow Demo recovery)
* [x] Adam : (100%)
* [ ] Brandon : (100%) (OpenFlow Demo recovery))
* [ ] David : (0%) (OpenFlow Demo recovery))
* [x] Jianying (15 min late): (100%)
* [ ] Paul : (0%)
* [ ] Alex : (92%)
* [ ] Nick : (100%)
* [x] Zeng Hongyi (James) - Workin with Alex (100%)
* [x] Pankaj Sharma - Working with Jianying on DDR (100%)

What are we building to build a community

  • Top priority - Build the NetFPGA user base
  • Means to this end (below)

New homepage mockup

Since the last meeting, (DevMeeting-2008_10_15), a new homepage mockup, on-line as: http://netfpga.org/home2.php, has been created that features key NetFPGA projects. A list of functions that the NetFPGA can be perform are listed on the main page, and each is linked to an on-line editable WordPress article. Each project has an icon, a short description, a list of key features, and a link to the Wiki page that provides full details. At the meeting this week, we will review the new pages with the goal of preparting to take this new content on-line. Relevant notes from last week are copied below.

In the meeting today, (DevMeeting-2008_10_22), we reviewed the web page and identified a set of improvements for the web page. We are now ready to have the final pages created. This is a task for a web designer, and we anticipate going again to Sherry to make the final changes in the pages.

Comments from the group today

  • Draft page: http://netfpga.org/home2.php
    • We need to fit the entire page on a 1024x768 browser window.
      • The buttons at the bottom need to fit on the page.
    • The NetFPGA = { image needs to be 25% smaller (for Adam)
    • The Font size for the applications need to consistent with the menu - Size=16 to 18 (for Adam)
    • The items in the menu system need to be text (for Sherry)
      • We need to be able to edit the menu options
      • The font in the menu need not match the font of the logo
      • A plain, sans-serif, Arial
      • The contrast (black/white/gray) needs to be highter
    • The link for * Anything Imaginable needs to be linked
    • The link for '15 countries' needs to be linked to the map
    • The top-bar of the Wordpress menu needs to be consistent with the main page (for sherry)
    • Icons should be shaded and consistent
  • We want to add an option for a referal form
    • Should be able to generate an email
      • Must look like a personalized email
      • The default message needs to look human initiated
      • Sample page: referral form
  • Comments from Nick after the meeting
    • Each project should list the regression tests
      • Needs to be in a human-readable form
      • But also needs to be completely consistent with the actual code
    • List of complete projects needs to appear
  • We need a rating system for the projects like VMWare

Adam


John

New pages (contributed 10/16/08)

New 2nd-Level pages

All of the pages also appear on the Blog as:

Brandon

  • (Not present at today's meeting)
  • (please update with link to script wiki page)
    • Add Detail here!
    • "NetFPGA is flexible, fast, and open platform for research, classroom, and commerical applications. There are N boards in M countries, used by Researchers with R tutorials in X countries". Calls to action - Learn more, Get Started, Develop
      • Also- Gigabit Ethernet Line Rate
    • Calls to action - Apps, Purchase, Events, Community, Docs, About
    • NetFPGA App store
      • Rating : **
        • Popularity, clicks, views, ...
      • Price : $Free (Gimick)
      • examples: sent via email (wiki upload failed)

Jianying

  • (Please update with links to pages)
    • Peer Project Table
      • Perhaps could be populated by Wiki data (See above from Adam)
      • Sample page: peer_projects
    • Referal Form (see email)
      • Must look like a personalized email
      • The default message needs to look human initiated
      • Sample page: referral form

RouterKit

  • Current status
    • Working and in the NetFPGA base package
  • Current users
    • None that have told us
  • How do we keep this up-to-date?
    • The project as is reads the arp and route entries form the proc file system
    • There should be little to no modifications needed in the future (only if the format in the proc file system changes)
    • If there are additional features needed then we would have to add those

Agilent Radio Interface (James)

  • Waiting for Antenna module from Agilent
  • Can start on state machines to generate packets
  • Suggested reviewing functionality in Traffic Generator
  • Will plan to have James review progress in two weeks (Nov. 5)

Update on Internet2 Deployments (Brandon)


Update on DDR2 (Jianying)

  • As of today - DDR2 memory is working
    • Asynchronous FIFO generated from Xilinx core
      • Read and write interfaces different
      • Empty interface on read interface operates differently in hardware than in simulation when the width of the datapaths were different
      • Work-around: Use the same width for both read and write interfaces, then the inconsistency between the simulation and hardware goes away.
      • Data Rate for aggregated read and write > 9 Gbps
        • Raw DDR2 runs at 200 MHz * 64 bits wide = 12.8 Gbps
        • Using 2034-byte block-size transfers
          • user logic: 1808 bytes of data + 226 byte of control word = 2034 bytes of data
          • DDR2: 14 bytes padding + 2034 bytes for user logic = 2048 bytes = 2KB DRAM block
          • 256 DDR2 clock cycles * 5ns / 8ns = 160 system clock cycles to read/write a block
        • Data size in DRAM = 2048 bytes
        • internal control byte (the extra, 9th byte per 8 bytes of packet data) is packed into the byte streams.
        • 15.0% cycles lost for arbitration and DDR2 access RAS and CAS latency
        • 2.6% cycles lost for DRAM refresh
        • Combining arbitration, DDR2 access latency and DRAM refresh, 17.6% cycles are lost, yielding a utilizable (100% - 17.6%) * 200 * 64 = 10540 M bps throughput to transfer data from/to DDR2 DRAM (half duplex). So 10.54 Gbps / 9 * 8 = 9.36 Gbps packet data throughput excluding the internal control byte is provided by the DDR2 block-of-data read/write module to the user logic in the system clock domain.
      • Documentation
  • Make the DRAM code available to other users
    • User1: Martin Labrecque (Toronto)
      • Wants DDR DRAM Controller
      • Would appreciate CORGEN settings and constraints
      • Jianying attached .UCF file (should be included in package)
      • Must be a packaged as a NGC because we can't release the Xilinx code
    • User2: Pankaj Sharma
      • Now has accounts on nf-test machine. (login=pankajs: uid=56620)
      • Jianying has checked the code into the tree
      • Check out as: svn co svn+ssh://nity.stanford.edu/hpn/home/svn/nf2/NF2/new_tree NF2
        • Enter password 3 times
      • cd NF2/lib/verilog/ddr2_blk_rdwr/src/
      • top module: ddr2_blk_rdwr.v
  • Instantiated Chipscope embedded in bitfile
    • Ran Chipscope GUI to view signals
    • Found the problem with the empty signal from Xilinx component
  • Still using hpn1 for debugging with Chipscope
  • Working to Bring Pankaj Sharma fully to speed with DDR2 Design

Preparing for the 1G General Release (All)

  • We should think about a general release of the NetFPGA code
  • Target Date: Mar 2009
  • Features
    • Register Interface - XML
      • Projects can overlap register address locations
      • Binaries would map addresses at compile-time
        • Hardware bitfile
          • List of modules loaded with versions
        • Software driver
          • Would need to verify that same modules and versions are loaded
      • Needs to be extensible
        • New projects should be able to add registers
        • New versions of a project should be able to add/remove registers
      • Glen and Jad have discussed specification
      • Perl code needs to generate Verilog and C from XML needs be implemented
    • CS-style student could implement this program from a clear specification
    • Configuration Script to verify configuration of lab of machines
    • YUM install is good
    • Use team-city to build packages
    • Regression test update
      • Use the verify test for regression test
      • Make it easier to write verification tests
      • Action/Delay for response mechanism is not clean


Upcoming Tutorials (John)

Google

  • Target audience
    • Network Engineers
  • Topics to add
    • RouterKit
  • Dates
    • TBD

South Korea

  • Hosts:
  • Laboratory Configuration
    • 20-30 machines (2-3 sets of 10 computers)
      • They will assemble the machines from those purchased in Korea
    • Expecting 40-90 people
      • Assign two-three people per machine
    • Dates of Event
      • Flight in: Arrive Sunday, Feb 22
      • Talk at KAIST: Mon, Feb 23 (100 miles from Seoul)
      • Setup: Tue Feb 24
      • Tutorial: Wed Feb 25 - Thr Feb 26
      • Return: After Feb 27
    • Travel Arrangments
      • Flight - Assume up to $1250, two people, reimbursed by CNU
      • Hotel - Rooms will be booked by CNU
    • Presentors: John, Glen
  • To Do
  • Email Discussions - Oct 4, 2008, "Re: NetFPGA tutorial in Korea"
  • Deadlines for lab setup: _________
  • Advertise with XUP

Toronto (Yashar)

  • Host: Yashar
  • Tentative Date: Dec. 2008
  • Equipment status: Has Lab ready

Upcoming Publications/Presentations

Traffic Generator (Adam)

  • Target for FCCM 2008
  • Alex would like a copy for Agilent

PC from Jordon (Alex)

  • Machine ordered
  • Will be delivered next week by ~Tuesday


Next Meeting

  • No meeting next week (Wed, Oct. 29) due to GENI
  • Next meeting in two weeks (Wed, Nov 5), at 8:30am
    • Jianying - Plan to show the documentation for DDR2 controller
    • Pankaj - Plan to talk about using the DDR2 memory interface
    • James - Plan to talk about packet generator for data stream
    • Glen and Jad - Plan to give an update on register interface specification

Additional Topics to Discuss

  • Add items here as needed
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