DevMeeting-2008 11 05

From NetFPGAWiki

Jump to: navigation, search

Agenda for NetFPGA Developers Meeting

  • Wednesday, Nov 5, 2008, 9am (This week only)

Major Agenda Topics

Contents

Role Call 

[x]=present, [ ]=MIA
(%)= Attendance over previous four meetings (10/8, 10/15, 10/22, Nov 5)
* [x] John : (100%)
* [ ] Glen : (50%) - MIA on Oct 22 & Nov 5
* [ ] Jad : (74%) - MIA on Nov 5
* [x] Adam : (100%)
* [ ] Brandon : (50%) - MIA on Oct 22 & Nov 5
* [ ] David : (0%) 
* [x] Jianying : (100%)
* [ ] Paul : (0%) 
* [X] Alex : (74%) - With Agilent group on Nov 5
* [ ] Nick : (50%) - MIA Oct 22, In Germany on Nov 5
* [x] Zeng Hongyi (James) - Workin with Alex (100%)
* [x] Pankaj Sharma - Working with Jianying on DDR (100%)

Wiki upgrade (Glen)

OpenFlow Practice Talk 3 (Jad)

  • Jad not present at this meeting on Nov. 5

RouterKit (Adam)

  • Current status
    • Working and in the NetFPGA base package
  • How to start program
    • run NF2/projects/router_kit/sw/rkd --help
  • How to verify it is running
    • route print
  • Regression tests
    • router_kit/regress
    • 5 tests
  • Current users
    • None that have told us
  • How do we keep this up-to-date?
    • The project as is reads the arp and route entries form the proc file system
    • There should be little to no modifications needed in the future (only if the format in the proc file system changes)
    • If there are additional features needed then we would have to add those

External Data Interface (James)

  • Documentation that describes the project and the developing plan
    • A recently built wiki page was removed due to manufacturer's concern..
    • Other Ways to share related information inside the group?
  • Basic Goal
    • Injecting Data from external device into Input Arbiter in the form of IP packet
    • 3 main steps: External Interface, Packetizing, Controlling
  • Suggested reviewing functionality in Traffic Generator
  • Learning on NetFPGA structure
    • Tutorial/Wiki Guide
    • Still challenging learning curve
  • Start on state machines to generate packets
    • Assumption: Data Stream is continuous, rather than busty.
    • A modified FIFO served as a packet generator
    • No complex state machines
    • Prototype packet generator drafted, need to comply with RFC791
      • Include timestamp or a sequence number
        • cycle # referenced from 125Mhz clk or 56 Ms clk
        • Sequence Number that increments with each packet sent
      • Add a UDP header (8 bytes) - Source Port, Dest. Port, Length
        • Defined by the register
        • Adam can give an example
        • CRC Checksum (start by using 0)
    • Additional details to be determined
      • I^2C control
      • AGC settings
      • LO
  • Alex will be at the meeting at 9am

Update on Internet2 Deployments (Brandon)

  • Not present on Nov 5
  • Brandon - Please update this section to describe progress since the last meeting.
  • Note past work is on-line as: GEC demo meeting notes for 10/15

Status of NetFPGA Cluster (Adam)

  • All 36? machines (less those used by David in Flash lab) upgraded to CentOS 5.2 w/latest kernel.
  • yum update on everything--OS, tools, and NetFPGA
  • 1 machine is set up for POMI

Update on DDR2 (Jianying)

  • Jianying- please update the text below
  • As of last week - DDR2 memory is working
    • Asynchronous FIFO generated from Xilinx core
      • Read and write interfaces different
      • Empty interface on read interface operates differently in hardware than in simulation when the width of the datapaths were different
      • Work-around: Use the same width for both read and write interfaces, then the inconsistency between the simulation and hardware goes away.
      • Data Rate for aggregated read and write > 9 Gbps
        • Raw DDR2 runs at 200 MHz * 64 bits wide = 12.8 Gbps
        • Using 2034-byte block-size transfers
          • user logic: 1808 bytes of data + 226 byte of control word = 2034 bytes of data
          • DDR2: 14 bytes padding + 2034 bytes for user logic = 2048 bytes = 2KB DRAM block
          • 256 DDR2 clock cycles * 5ns / 8ns = 160 system clock cycles to read/write a block
        • Data size in DRAM = 2048 bytes
        • internal control byte (the extra, 9th byte per 8 bytes of packet data) is packed into the byte streams.
        • 15.0% cycles lost for arbitration and DDR2 access RAS and CAS latency
        • 2.6% cycles lost for DRAM refresh
        • Combining arbitration, DDR2 access latency and DRAM refresh, 17.6% cycles are lost, yielding a utilizable (100% - 17.6%) * 200 * 64 = 10540 M bps throughput to transfer data from/to DDR2 DRAM (half duplex). So 10.54 Gbps / 9 * 8 = 9.36 Gbps packet data throughput excluding the internal control byte is provided by the DDR2 block-of-data read/write module to the user logic in the system clock domain.
      • Documentation
  • Make the DRAM code available to other users
    • User1: Martin Labrecque (Toronto)
      • Wants DDR DRAM Controller
      • Would appreciate CORGEN settings and constraints
      • Jianying attached .UCF file (should be included in package)
      • Must be a packaged as a NGC because we can't release the Xilinx code
    • User2: Pankaj Sharma
      • Now has accounts on nf-test machine. (login=pankajs: uid=56620)
      • Jianying has checked the code into the tree
      • Check out as: svn co svn+ssh://nity.stanford.edu/hpn/home/svn/nf2/NF2/new_tree NF2
        • Enter password 3 times
      • cd NF2/lib/verilog/ddr2_blk_rdwr/src/
      • top module: ddr2_blk_rdwr.v
  • Instantiated Chipscope embedded in bitfile
    • Ran Chipscope GUI to view signals
    • Found the problem with the empty signal from Xilinx component
  • Still using hpn1 for debugging with Chipscope
  • Working to Bring Pankaj Sharma fully to speed with DDR2 Design
  • Next step: build a DRAM FIFO for packet pipeline
    • Interchange with BlockRAM or SRAM Output Queues
    • include.txt : specify library module for output queue
      • output queue code in nf2/lib/verilog/output_queues/src/{ BRAM, SRAM, }

Preparing for the 1G General Release (All)

  • Glen/Jad not present for Nov 5 Meeting
  • We should think about a general release of the NetFPGA code
  • Target Date: Mar 2009
  • Features
    • Register Interface - XML
      • Projects can overlap register address locations
      • Binaries would map addresses at compile-time
        • Hardware bitfile
          • List of modules loaded with versions
        • Software driver
          • Would need to verify that same modules and versions are loaded
      • Needs to be extensible
        • New projects should be able to add registers
        • New versions of a project should be able to add/remove registers
      • Glen and Jad have discussed specification
      • Perl code needs to generate Verilog and C from XML needs be implemented
    • CS-style student could implement this program from a clear specification
    • Configuration Script to verify configuration of lab of machines
    • YUM install is good
    • Use team-city to build packages
    • Regression test update
      • Use the verify test for regression test
      • Make it easier to write verification tests
      • Action/Delay for response mechanism is not clean

Register Interface - Specifications (Glen and Jad)

  • New Register Interface Specification


Upcoming Tutorials (John)

Toronto (Yashar)

  • Host: Yashar
  • Tentative Date: Dec. 2008
  • Equipment status: Has Lab ready

South Korea - Feb 23-27, 2009

  • Hosts:
  • Laboratory Configuration
    • 20-30 machines (2-3 sets of 10 computers)
      • They will assemble the machines from those purchased in Korea
    • Expecting 40-90 people
      • Assign two-three people per machine
    • Dates of Event
      • Flight in: Arrive Sunday, Feb 22
      • Talk at KAIST: Mon, Feb 23 (100 miles from Seoul)
      • Setup: Tue Feb 24
      • Tutorial: Wed Feb 25 - Thr Feb 26
      • Return: After Feb 27
    • Travel Arrangments
      • Flight - Assume up to $1250, two people, reimbursed by CNU
      • Hotel - Rooms will be booked by CNU
    • Presentors: John, Glen
  • To Do
  • Email Discussions - Oct 4, 2008, "Re: NetFPGA tutorial in Korea"
  • Deadlines for lab setup: _________
  • Advertise with XUP

Japan - Mar 1, 2009 or Feb 15, 2009

  • Feb 15 or March 1 (Week before or after Korea)
  • University of Tokyo - Aki Nakao (Princeton PlanetLab developer)

Google - March 2009?

  • January or March 2009 (TBD)
  • Target audience: Network Engineers
  • Topics to add: RouterKit

Upcoming Publications/Presentations

  • Traffic Generator (Adam)
    • Target for FCCM 2008
    • Alex would like a copy for Agilent

PC from Jordon (Alex)

  • Machine has been delivered

Additional Topics to Discuss

  • Add items here as needed
Retrieved from "http://netfpga.org/netfpgawiki/index.php/DevMeeting-2008_11_05"
Personal tools