DevMeeting-2008 11 12

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Agenda for NetFPGA Developers Meeting

  • Wednesday, Nov 12, 2008, 8:30am

Major Agenda Topics

Contents

Building the NetFPGA Community

  • New Cards shipping this week

New Web page

  • Draft page: http://netfpga.org/home2.php
    • We need to fit the entire page on a 1024x768 browser window.
      • The buttons at the bottom need to fit on the page.
    • The NetFPGA = { image needs to be 25% smaller (for Adam)
    • The Font size for the applications need to consistent with the menu - Size=16 to 18 (for Adam)
    • The items in the menu system need to be text (for Sherry)
      • We need to be able to edit the menu options
      • The font in the menu need not match the font of the logo
      • A plain, sans-serif, Arial
      • The contrast (black/white/gray) needs to be highter
    • The link for * Anything Imaginable needs to be linked
    • The link for '15 countries' needs to be linked to the map
    • The top-bar of the Wordpress menu needs to be consistent with the main page (for sherry)
    • Icons should be shaded and consistent
  • We want to add an option for a referal form
    • Should be able to generate an email
      • Must look like a personalized email
      • The default message needs to look human initiated
      • Sample page: referral form
  • Comments from Nick after the meeting
    • Each project should list the regression tests
      • Needs to be in a human-readable form
      • But also needs to be completely consistent with the actual code
    • List of complete projects needs to appear


Adam


John

New pages (contributed 10/16/08)

New 2nd-Level pages

All of the pages also appear on the Blog as:

Brandon

  • (Not present at today's meeting)
  • (please update with link to script wiki page)
    • Add Detail here!
    • "NetFPGA is flexible, fast, and open platform for research, classroom, and commerical applications. There are N boards in M countries, used by Researchers with R tutorials in X countries". Calls to action - Learn more, Get Started, Develop
      • Also- Gigabit Ethernet Line Rate
    • Calls to action - Apps, Purchase, Events, Community, Docs, About
    • NetFPGA App store
      • Rating : **
        • Popularity, clicks, views, ...
      • Price : $Free (Gimick)
      • examples: sent via email (wiki upload failed)

Jianying

  • (Please update with links to pages)
    • Peer Project Table
      • Perhaps could be populated by Wiki data (See above from Adam)
      • Sample page: peer_projects
    • Referal Form (see email)
      • Must look like a personalized email
      • The default message needs to look human initiated
      • Sample page: referral form

Draft Script for NetFPGA Video (John)

  • Review at the meeting

Feedback on the ANCS OpenFlow talk (for Jad)

  • Burst period load interval

Recent Web Upgrades

RouterKit

  • Status:
    • Fully Working
    • Included in NetFPGA base package
  • How to start program
    • run NF2/projects/router_kit/sw/rkd --help
  • How to verify it is running
    • route print
  • Regression tests
    • router_kit/regress
    • 5 tests
  • Current users
    • None that have told us
  • How do we keep this up-to-date?
    • The project as is reads the arp and route entries form the proc file system
    • There should be little to no modifications needed in the future (only if the format in the proc file system changes)
    • If there are additional features needed then we would have to add those

External Data Interface (James)

  • Basic Goal
    • Injecting Data from external device into Input Arbiter in the form of Ethernet Frame (A new Rx Queue)
    • 3 main steps: External Interface, Packetizing, Controlling
  • Packet Style (following Ethernet, IPv4, UDP packet headers)
CTRL + Bits 0–7 8–15 16–23 24–31 32–39 40–47 48–55 56–63
0xFF 0 port_dst 16 (all zero) word_length 16 port_src 16 byte_length 16
0x00 64 mac_dst 48 mac_src_hi 16
0x00 128 mac_src_lo 32 mac_ethertype 16 ip_version 4 ip_header_length 4 ip_ToS 8
0x00 192 ip_total_length 16 ip_id 16 ip_flags 3 + ip_flag_offset 13 ip_ttl 8 ip_prot 8
0x00 256 ip_header_checksum 16 ip_src 32 ip_dst_hi 16
0x00 320 ip_dst_lo 16 udp_src 16 udp_dst 16 udp_length 16
0x00 384 udp_checksum 16 RESERVED 16 sequence_num 32
0x00 448 DSP result 32 DSP result 32
0x00 512 DSP result 32 DSP result 32
0x00 ... ...
0x10 - CRC Checksum 32
  • Features
    • 32 bit DSP results
    • Void Ethernet header and CRC checksum
    • A UDP header (8 bytes) - Source Port, Dest. Port, Length
    • Sequence Number that increments with each packet sent
    • Additional details to be determined
      • I^2C control
      • AGC settings
      • LO
  • Progress
    • Prototype packet generator drafted
    • All fields are hard-coded
  • Action Items
    • Interface to 4 Registers: Payload length, UDP dest, IP src, IP dest
    • SRAM interface for testing: DSP results -> Ethernet Frame

Update on Internet2 Deployments (Brandon)

  • Not present on Nov 5
  • Brandon - Please update this section to describe progress since the last meeting.
  • Note past work is on-line as: GEC demo meeting notes for 10/15

Status of NetFPGA Cluster (Adam)

  • Adam - Please revised and update the text below
  • All 36? machines (less those used by David in Flash lab) upgraded to CentOS 5.2 w/latest kernel.
  • yum update on everything--OS, tools, and NetFPGA
  • 1 machine is set up for POMI

Update on DDR2 (Jianying)

  • Jianying- please revised and update the text below
  • As of last week - DDR2 memory is working
    • Asynchronous FIFO generated from Xilinx core
      • Read and write interfaces different
      • Empty interface on read interface operates differently in hardware than in simulation when the width of the datapaths were different
      • Work-around: Use the same width for both read and write interfaces, then the inconsistency between the simulation and hardware goes away.
      • Data Rate for aggregated read and write > 9 Gbps
        • Raw DDR2 runs at 200 MHz * 64 bits wide = 12.8 Gbps
        • Using 2034-byte block-size transfers
          • user logic: 1808 bytes of data + 226 byte of control word = 2034 bytes of data
          • DDR2: 14 bytes padding + 2034 bytes for user logic = 2048 bytes = 2KB DRAM block
          • 256 DDR2 clock cycles * 5ns / 8ns = 160 system clock cycles to read/write a block
        • Data size in DRAM = 2048 bytes
        • internal control byte (the extra, 9th byte per 8 bytes of packet data) is packed into the byte streams.
        • 15.0% cycles lost for arbitration and DDR2 access RAS and CAS latency
        • 2.6% cycles lost for DRAM refresh
        • Combining arbitration, DDR2 access latency and DRAM refresh, 17.6% cycles are lost, yielding a utilizable (100% - 17.6%) * 200 * 64 = 10540 M bps throughput to transfer data from/to DDR2 DRAM (half duplex). So 10.54 Gbps / 9 * 8 = 9.36 Gbps packet data throughput excluding the internal control byte is provided by the DDR2 block-of-data read/write module to the user logic in the system clock domain.
      • Documentation
  • Make the DRAM code available to other users
    • User1: Martin Labrecque (Toronto)
      • Wants DDR DRAM Controller
      • Would appreciate CORGEN settings and constraints
      • Jianying attached .UCF file (should be included in package)
      • Must be a packaged as a NGC because we can't release the Xilinx code
    • User2: Pankaj Sharma
      • Now has accounts on nf-test machine. (login=pankajs: uid=56620)
      • Jianying has checked the code into the tree
      • Check out as: svn co svn+ssh://nity.stanford.edu/hpn/home/svn/nf2/NF2/new_tree NF2
        • Enter password 3 times
      • cd NF2/lib/verilog/ddr2_blk_rdwr/src/
      • top module: ddr2_blk_rdwr.v
  • Instantiated Chipscope embedded in bitfile
    • Ran Chipscope GUI to view signals

Using the DDR2 Memory (Pankaj)

  • Progress with DRAM FIFO for packet pipeline
    • Interchange with BlockRAM or SRAM Output Queues
    • include.txt : specify library module for output queue
      • output queue code in nf2/lib/verilog/output_queues/src/{ BRAM, SRAM, }


Register Interface - Specifications (Glen and Jad)

  • New Register Interface Specification


Upcoming Tutorials (John)

Toronto (Yashar)

  • Host: Yashar
  • Tentative Date: Dec. 2008
  • Equipment status: Has Lab ready

South Korea - Feb 23-27, 2009

  • Hosts:
  • Laboratory Configuration
    • 20-30 machines (2-3 sets of 10 computers)
      • They will assemble the machines from those purchased in Korea
    • Expecting 40-90 people
      • Assign two-three people per machine
    • Dates of Event
      • Flight in: Arrive Sunday, Feb 22
      • Talk at KAIST: Mon, Feb 23 (100 miles from Seoul)
      • Setup: Tue Feb 24
      • Tutorial: Wed Feb 25 - Thr Feb 26
      • Return: After Feb 27
    • Travel Arrangments
      • Flight - Assume up to $1250, two people, reimbursed by CNU
      • Hotel - Rooms will be booked by CNU
    • Presentors: John, Glen
  • To Do
  • Email Discussions - Oct 4, 2008, "Re: NetFPGA tutorial in Korea"
  • Deadlines for lab setup: _________
  • Advertise with XUP

Japan - Mar 1, 2009 or Feb 15, 2009

  • Feb 15 or March 1 (Week before or after Korea)
  • University of Tokyo - Aki Nakao (Princeton PlanetLab developer)

Google - March 2009?

  • January or March 2009 (TBD)
  • Target audience: Network Engineers
  • Topics to add: RouterKit

Upcoming Publications/Presentations

  • Traffic Generator (Adam)
    • Target for FCCM 2008
    • Alex would like a copy for Agilent

PC from Jordon (Alex)

  • Machine has been delivered

Preparing for the 1G General Release (All)

  • Glen/Jad not present for Nov 5 Meeting
  • We should think about a general release of the NetFPGA code
  • Target Date: Mar 2009
  • Features
    • Register Interface - XML
      • Projects can overlap register address locations
      • Binaries would map addresses at compile-time
        • Hardware bitfile
          • List of modules loaded with versions
        • Software driver
          • Would need to verify that same modules and versions are loaded
      • Needs to be extensible
        • New projects should be able to add registers
        • New versions of a project should be able to add/remove registers
      • Glen and Jad have discussed specification
      • Perl code needs to generate Verilog and C from XML needs be implemented
    • CS-style student could implement this program from a clear specification
    • Configuration Script to verify configuration of lab of machines
    • YUM install is good
    • Use team-city to build packages
    • Regression test update
      • Use the verify test for regression test
      • Make it easier to write verification tests
      • Action/Delay for response mechanism is not clean


Contributors 

[x]=present, [ ]=Not Present
* [X] John 
* [X] Glen 
* [-] Jad - Late 45 min
* [X] Adam 
* [ ] Brandon 
* [ ] David  
* [X] Jianying 
* [ ] Paul  
* [X] Alex 
* [X] Nick 
* [X] Zeng Hongyi (James) - Workin with Alex 
* [X] Pankaj Sharma - Working with Jianying on DDR
* [X} Tatsuya (OpenFlow)

Additional Topics to Discuss

  • Add items here as needed
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