Simulation Environment

From NetFPGAWiki

Contents 1 Requirements 2 Environment 2.1 DDR Controller 3 Simulators 3.1 ModelSim SE 3.2 Synopsys VCS 3.3 Perl glue

Requirements

The environment must provide the ability to simulate:

• register reads/writes from host
• packet transmission/reception via the Ethernet interfaces
• DMA transfers to/from host (new)
• SRAM
• DDR2 DRAM (new)

Highly desirable, but not essential initially, is the ability to simulate:

• PowerPC/MicroBlaze (new?)

The environment should:

• be scriptable
• allow tests to be run non-interactively for acceptance/regression testing
• provide a GUI for debugging

Environment

DDR Controller

The DDR controller waits for 200μs after reset for the DDR memory to complete power-up initialization. The simulation environment overrides this wait period to reduce simulation times.

Simulators

ModelSim SE

ModelSim SE will be the default simulator for NetFPGA 2.1.

Advantages:

• Runs under Windows and Linux

Disadvantages:

• need to recreate simulation environment from scratch

Questions:

• How do we integrate ModelSim with scripts?

ModelSim setup

Synopsys VCS

Advantages:

• current environment based on VCS

Disadvantages:

• users must obtain VCS in addition to the Xilinx tools
• VCS is hard to work with in terms of usability (jad)

Perl glue

The Perl scripts do two main things:

1. Generate text files used as input to the Verilog simulation. These text files describe :
   • packets that should arrive at the system, and when they should arrive.
   • PCI bus events (writes and reads)
2. Checks the transmitted packets against a text file containing a list of expected packets. Some form of automatic checking is essential. The current Perl checker allows you to specify the exact order in which packets should be transmitted, or else no order. I find the latter to be most useful.