SummerCamp2008

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NetFPGA Summer Camp

  • Gates Building, Room 104, 353 Serra Mall, Stanford, CA 94305
  • Aug 4-8, 2008
  • Event Description

Locations

People

Daily Schedule (Monday-Friday, Aug 4-8, 2008)

  • 8:30am: Breakfast (provided) in Gates room 104
  • 9am-10:30am: Instruction Session 1
  • 10:30am-11am: Morning Break
  • 11am-12:30pm: Instruction Session 2
  • 12:30p-1:30pm: Lunch (provided)
  • 1:30p-3pm: Instruction Session 3
  • 3:00pm-3:30pm: Afternoon Break
  • 3:30pm-5:30pm: Instruction Session 4
  • 6:30pm: Dinners are planned on the following nights
    • Monday: Pizza - AT&T Patio of the Gates Building
    • Tuesday: Group Dinner at MacArthur Park (near Palo Alto CalTrain station)
      • Shuttle at 8:30pm returns to SLAC
    • Friday: California Cafe (near the Historic Stanford Barn)
      • Shuttle at 8:30pm returns to SLAC


Weekday Event Detail

Sunday, Aug 3

Monday, Aug 4

  • Welcome and introductions (All)
  • Day 1 (John, Glen, Adam)
    • Background
      • Basics of an IP Router
      • The NetFPGA hardware
      • How people use the NetFPGA
      • Why people use the NetFPGA
    • The Stanford Base Reference Router
      • Inside the NetFPGA hardware
      • Introduction to FPGAs and Verilog
    • The Enhanced Reference Router
      • Buffer sizing requirements in a router
      • Observering and controlling the queue size
    • Life of a packet through the NetFPGA
      • Data and control planes
      • Interface to software: Exceptions and Host I/O
    • Demonstration of the NetFPGA
      • Address Lookup
      • PW-OSPF
      • Java-based Graphical User Interface (GUI)
      • Demonstration of High Definition (HD) video streaming
    • Slides: Image:NetFPGA Summer Camp-Day1.pdf
  • Pizza dinner: AT&T Patio of the Gates Building

Tuesday, Aug 5

  • Module Development and Testing
    • Running ModelSim with the NetFPGA TestBench (Glen)
      • Compile, simulate, view waveforms
      • Example: Simply Encryption on a packet payload
      • Scrambling the payload with XOR using a key from a register
    • Regression testing to verify hardware functionality (Adam)
      • Synthesize and run the hardware
      • Verify value: 0xFFFFFFFF (would invert every bit of every byte of payload)
      • Verify value: 0xFF00FF00 (would invert every other byte of payload)
      • Verify value: 0x55555555 (would invert every other bit of payload)
    • Slides: Image:NetFPGA Summer Camp-Module Development and Testing.pdf
  • Introduction to OpenFlow (Jad)
  • Group Dinner at MacArthur Park

Wednesday, Aug 6

  • Group discussion
    • Projects ideas
    • Scope of work that can be accomplished in 2-3 days
  • Team up for Projects
    • Project leaders will describe projects
    • Group will provide feedback on the scope
    • Be sure to have one hardware designer per team
  • Precise Time Protocol (PTP) (Sara)
    • Background and review of block diagrams
    • Show PTP running on nf-test machines
    • Show syncronization of pairs of machines
    • Discuss relevent Verilog Code

Ideas for Long Term Projects

  • Enhance Reference Router to support IPv6
  • Enhance Traffic Generator to send TCP packets
  • Valiant Load Balancing
  • Graphical User Interface (like CLACK)
  • MAC-in-MAC Encapsulation
  • Encryption / Decryption modules
  • RCP Transport Protocol
  • Packet Filtering ( Firewall, IDS, IDP )
  • TCP Offload Engine
  • DRAM Packet Queues
  • 8-Port Switch using SATA Bridge
  • Build our own MAC (from source, rather than core)
  • Use XML for Register Definitions

Ideas for Short-term Projects

  • A software component
  • Enhanced Java GUI
  • Hardware enhancement
  • Simple Ethernet 1Gbps MAC
  • SummerCamp_2008_Projects: Add your information here

Thursday, Aug 7

  • Work on Projects
  • NetFPGA group available for Questions and Answers

Friday, Aug 8

  • Complete Projects
  • Award prizes to winning projects
  • Group Dinner at California Cafe

Saturday, Aug 9

  • Checkout of Stanford Guest House

Background Reading

Pre-event Exercise

Before you arrive, please complete the following assigment

  • Background
    • Identify the acronyms for SCONE and HCORR in the context of the NetFPGA Reference Desing.
    • Hint: See the on-line NetFPGA Guide for help.
      • Identify the acronym for SCONE and list three key funtions it performs:
      • Identify the acronym for HCORR and list three key functions it performs: 
 S_______ C_______ O_______ NE______
 performs:
 1)
 2)
 3)

 H_______ C_______ O________ R_______ R_______
 performs:
 1)
 2)
 3)


  • The basic reference router
    • Consider a network packet transported through a hardware pipeline.
    • On each clock cycle, eight bytes (64 bits) moves between Flip/Flops
    • The data that streams through the pipeline includes:
      • A shim
      • An Ethernet MAC header
      • IPv4 header
      • The Packet payload.
    • Additional signals are provided to indicate the start of the packet and headers
      • Assuming an an 8-byte shim, a standard Ethernet header, a standard IPv4 header (without options), and a 120 byte packet payload, how many clock cycles are needed to forward a packet through the pipeline? 
   _______ Clocks
  • Simple coding with Verilog
    • Assume that input data arrives on an eight-byte bus as: in_data[63:0]
    • Assume that the IP Destination address should go into a 32-bit register named: dst_ip
    • Assume that dst_ip is split between two in_data words.
      • Write the verilog statement that assigns the first two bytes of dst_ip to the last two bytes of in_data.
      • Write the verilog statement that assigns the last two bytes of dst_ip to the first two words of the the in_Data that appears on the next clock
      • Write the verilog code that determines if an IP destination of a packet matches 141.142.2.2
  • Hint: See: The Verilog Golden Reference Guide by Doulos for help with Verilog syntax. 
 dst_ip[ 31 : ?? ] <= in_data[ ?? : ??] ; // on a given clock
   ...
 dsp_ip[    :    ] <= in_data[ ?? : ??] ; // on the next clock
   ..
 if dsp_ip[31:0] ?? ?? ??  // Compare address to hex equivalent of 141.142.2.2

Tools

  • When you arrive at the workshop, you will be provided a nf-test machine and the code for a test bench were you can insert your code, compile the Verilog, and simulate the code with ModelSim.
  • If you woul like to compile and synthesize your code before you arrive, you can download and install ModelSim for circuit simulation.
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