MACinMAC

Description: MACinMAC simple implementation for 2008 SummerCamp project
Suggestor: Jim chen, Tatsuya Yabe, Hao Chen
Team Leader: Hao Chen
Wiki notes: Summer08Project-MinM

Hardware-Accelerated Mathematics Library for NetFPGA

Description: C library and associated hardware shims to allow use of Xilinx Coregen mathematics IP on NetFPGA. Framework will use multiple transports (DMA, Eth) to distribute computation units to one or more NetFPGA boards.
Demonstration: Team hopes to demonstrate acceleration of matrix multiplication and FFT operations on the NetFPGA using this new library. May demonstrate parallel processing by two NetFPGA hosts.
Team: Dan Bedard, Will Tetteh, Yufeng Xin

802.1q (VLAN)s

Description: Modify the reference router to support VLAN (.1q) tagging on the interfaces. Enable routing, so that the router can have "logical" vlan-based interfaces on top of the physical interface. (ie, a single physical interface could have many IP subnets assigned).
Suggester/Team Leader: Steve Padgett
Team Members: Steve Padgett, Bilal Anwer, David Miller, Ke Xiang, Carson Stuart, Michael Blodgett
URL: SummerCamp2008-Dot1Q

Heavy Hitter Identification using Multistage filters

Description: We wish to idenfity top most flows by hashing the incoming flows into using multistage filters in the SRAM. The entries that match all the filters would be updated in the register file which would be read in by the software.
Suggestor: Faisal Khan,Guan Yo and Atif
URL: Paper [1]

Layer 2 Load Balancing

Description: Perform Layer-2 traffic load balancing between 'n' servers. A virtual MAC address will be used as common destination on the input port and MAC translation will be performed by the balancer. Also, the balancer should be able to reply to ARP requests, informing about the virtual MAC used.
Team Members: Danai Chasaki, Fernando Hammerli, Paul Germano

Pattern Matching / "Mini-IDS"

Description: Scan packet payload for byte sequences and detect when patterns match. Configurable actions when a packet matches a pattern: count or drop. Pattern(s) to detect and match actions specified by registers.
Team: Young Cho, Nathan Schrenk
URL: none yet

TCP Traffic Analysis for Passive End-to-End Bandwidth Measurement

Description: Measure delay between arrival of packets of TCP flow and deduce the bottleneck bandwidth.
Suggestor: Jon Lei
Team: Martin Zadnik, Yaping Zhu
URL: http://lion.cs.uiuc.edu/group_seminar_slides/Packet_dispersion_Dovrolis-1.ppt

Assessment of Prototyping an AFDX Policy Switch Leveraging NetFPGA, Ethane, and OpenFlow Switch

Description

Assess feasibility of NetFPGA and IP research components to prototype AFDX

Top level protocol behavior comparison Ethane vs AFDX

Major differences and design scope

Notional Architecture

Allocation of reuse proposed

Suggestor

Tom Gaska

Task Dependencies

AFDX Reference Specification

Configured NetFPGA System with Reference Tutorials – Support from Adam planned for later today

Access to Ethane IP – Glen investigating

Thesis and Architecture NetFPGA Description

Ethane NetFPGA HW/SW Implementation

Meeting with Implementation member

Access to OpenFlow IP – Glen Investigating

Specification and NetFPGA Architecture Description

OpenFlow NetFPGA HW/SW Implementation

ntop on NetFPGA

Description: ntop is a network traffic probe that shows the network usage, similar to what the popular top Unix command does. From the file deri-10g.pdf below, ntop run on Endace DAG. Running ntop on Dual Xeon rack server with internet traffic of 200 Mb/s consumes about 50%-60% of CPU time. Shall we expect porting ntop to be able to run on NetFPGA and take off almost the load of CPU? And will NetFPGA will perform better on the same PC, or how it will be comparable to Endace DAG.

With 4 Gigabit Ethernet ports on NetFPGA, these will be simply used for fanning-out single mirror port on any commercial Gigabit Ethernet switch, which has only single port, to be tapped for other application probes, for example, netflow, nids, etc.