Tokyo Tutorial 2011 (near CoNext)

Informational Tutorial

Presented by: G. Adam Covington, Tatsuya Yabe

Date: Monday, December 5, 2011

Time: 1pm - 5pm

Location: IIJ (Internet Initiative Japan) Seminar room #2, 17th floor
Jinbocho Mitsui Bldg., 1-105 Kanda Jinbo-cho, Chiyoda-ku, Tokyo, 101-0051, Japan
Location Map

Abstract

The NetFPGA is and open platform enabling researchers and instructors to build high-speed, hardware-accelerated networking systems. The platform can be used in the classroom to teach students how to build Ethernet switches and Internet Prototcol (IP) routers using hardware rather than software. The platform can be used by researchers to prototype advanced services for next-generation networks.

By using Field Programmable Gate Arrays (FPGAs), the NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained. During the tutorial, attendees will learn about the NetFPGA platform and and how it can be used. We will demonstrate the use of the reference router to dynamically re-route traffic using PW-OSPF with streaming video traffic. We will also show how we can extend existing designs to experiment with buffer sizes.

No knowledge of Verilog/VHDL is required to attend the tutorial, although knowledge of these languages is needed to program NetFPGA.

Outline

  • Introduction to the Platform

    • Users (Professors & Researchers)

    • What is the NetFPGA

      • Board
      • Tools & Reference Designs
      • Contributed Projects
      • Community
  • Hardware Overview

    • NetFPGA 1G

      • Gigabit Ethernet interfaces
      • Field Programmable Gate Array (FPGA) Logic
      • Random Access Memory (RAM)
      • PCI interface
    • NetFPGA 10G

      • SPF+ interfaces
      • Field Programmable Gate Array (FPGA) Logic
      • Random Access Memory (RAM)
      • PCIe interface
  • Brief recap if IP/Routing

  • Example 1: Basic Functionality (reference router)

    • PW-OSPF

    • Routing Tables

    • Dynamic re-routing

  • Example 2: Advanced Functionality (buffer sizing based on reference router)

    • Brief introduction of buffer sizing

      • Rule-of-thumb for the buffer size
      • Round-trip propation delay
      • Capacity of bottlneck link
      • Number of active flows
    • Additional hardware

      • Event capture module
      • Rate limiter
    • Experiments

      • Netperf
      • HD video transport

    Where to get started/What to do next

    • Webpage

    • Wiki

    • Forums

About the presentors

  • Adam Covington

    Adam is a Research Associate of the High-Performance Network Group (HPN) at Stanford University. He is currently working on the NetFPGA project, which enables researchers and instructors to build hardware-accelerated networking systems. Previously, he was a Research Associate with the Reconfigurable Network Group (RNG) at Washington University in St. Louis. While at Washington University he designed, and implemented clustering algorithms on FPGAs and supported a hardware accelerated classification system on the FPX platform. Adam’s current research interests include reconfigurable systems, artificial intelligence (clustering and classification), and applications of artificial intelligence algorithms. Adam completed a Bachelor of Science degree in Computer Engineering from Western Michigan University in April 2003 and accepted a Distinguished Masters of Science Fellowship from Washington University. He completed his Masters of Science degree in Computer Science and Engineering from Washington University in December 2006. Adam continues to provide support for the NetFPGA project which includes helping users worldwide as well as arranging and presenting tutorials.

  • Tatsuya Yabe

    Tatsuya Yabe is a visiting researcher of the High-Performance Network Group (HPN) at Stanford University. He joined the group in 2008, and since then he has been closely working with the NetFPGA development team. He also is an Assistant Manager of System Platforms Research Labs in NEC. Previously he was a hardware engineer in NEC Communication Systems. There, he successfully designed over a dozen FPGAs as well as circuit boards for large telecommunication carriers. He now owns several NetFPGA projects including an OpenFlow implementation. He assisted the NetFPGA summer camp in 2010 and 2011.

Schedule
1:00-3:00tutorial session
3:00-3:30coffee break
3:30-5:00tutorial session

Registration

Before November 7, 2011:

  • Student $100
  • Attendee $200

November 7, 2011 and after
  • Student $150
  • Attendee $250

Students must email a copy of their Student ID to gcoving@stanford.edu:w

Register here to attend