Toronto Tutorial 2011 (near SIGCOMM)

Informational Tutorial

Presented by: Andrew W. Moore, G. Adam Covington

Date: Friday, August 19, 2011

Time: 8am - 12pm

Location:Pier 2/3 3rd floor, Westin Harbour Castle
Toronto, Canada

Abstract

An open platform called the NetFPGA has been developed at Stanford University. The NetFPGA platform enables researchers and instructors to build high-speed, hardware-accelerated networking systems. The platform can be used in the classroom to teach students how to build Ethernet switches and Internet Prototcol (IP) routers using hardware rather than software. The platform can be used by researchers to prototype advanced services for next-generation networks.

By using Field Programmable Gate Arrays (FPGAs), the NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained. During the tutorial, we will use the NetFPGA to determine the amount of memory needed to buffer TCP/IP data streaming through the Gigabit/second router. Hardware circuits within the NetFPGA will be implemented to measure and plot the occupancy of buffers. Circuits will be downloaded into reconfigurable hardware and tested with live, streaming Internet video traffic.

NetFPGA Tutorial

Outline

  • Introduction to the Platform

    • Users (Professors & Researchers)

    • What is the NetFPGA

      • Board
      • Tools & Reference Designs
      • Contributed Projects
      • Community
  • Hardware Overview

    • NetFPGA 1G

      • Gigabit Ethernet interfaces
      • Field Programmable Gate Array (FPGA) Logic
      • Random Access Memory (RAM)
      • PCI interface
    • NetFPGA 10G

      • SPF+ interfaces
      • Field Programmable Gate Array (FPGA) Logic
      • Random Access Memory (RAM)
      • PCIe interface
  • Brief recap if IP/Routing

  • Example 1: Basic Functionality (reference router)

    • PW-OSPF

    • Routing Tables

    • Dynamic re-routing

  • Example 2: Advanced Functionality (buffer sizing based on reference router)

    • Brief introduction of buffer sizing

      • Rule-of-thumb for the buffer size
      • Round-trip propation delay
      • Capacity of bottlneck link
      • Number of active flows
    • Additional hardware

      • Event capture module
      • Rate limiter
      • Delay module
    • Experiments

      • Netperf
      • HD video transport

    Where to get started/What to do next

    • Webpage

    • Wiki

    • Forums

About the presentors

  • Andrew W. Moore

    Andrew W. Moore is a Lecturer at the University of Cambridge Computer Laboratory. He joined the permanent faculty of Cambridge in 2007, prior to this he had been an EPSRC Roberts Fellow at Queen Mary, University of London, an Intel Research Fellow in Cambridge and foundation-researcher at the Cambridge Marconi research laboratory. Throughout this time Andrew has focused upon network characterisation and measurement, extensible monitoring for application performance-analysis and large-scale Internet monitoring and emulation. Interest in switch design has led to work in physical line-coding for optical networks, and novel optical-switch architectures.

    Andrew completed his Ph.D. with the Cambridge University Computer Laboratory in 2001 and prior to that took a Masters degree and an honours degree from Monash University in Melbourne. Australia. Alongside routine collaboration with AT&T, Endace, Intel, and Microsoft, Andrew Moore has served as principal investigator on grants from the UK Research Council (EPSRC) and a number of UK government bodies. He is a chartered engineer with the IET and a member of the IEEE, ACM and USENIX.

  • Adam Covington

    Adam is a Research Associate of the High-Performance Network Group (HPN) at Stanford University. He is currently working on the NetFPGA project, which enables researchers and instructors to build hardware-accelerated networking systems. Previously, he was a Research Associate with the Reconfigurable Network Group (RNG) at Washington University in St. Louis. While at Washington University he designed, and implemented clustering algorithms on FPGAs and supported a hardware accelerated classification system on the FPX platform. Adam’s current research interests include reconfigurable systems, artificial intelligence (clustering and classification), and applications of artificial intelligence algorithms. Adam completed a Bachelor of Science degree in Computer Engineering from Western Michigan University in April 2003 and accepted a Distinguished Masters of Science Fellowship from Washington University. He completed his Masters of Science degree in Computer Science and Engineering from Washington University in December 2006. Adam continues to provide support for the NetFPGA project which includes helping users worldwide as well as arranging and presenting tutorials.

Schedule
8:00-10:00tutorial session
10:00-10:30coffee break
10:30-12:00tutorial session

Registration

Cost of the tutorial is $150. Register here to attend