NetFPGA Beijing Tutorial

Hands-on with the to build a Gigabit-rate Router at Beijing Jaiotong University

Presented by: John W. Lockwood and Jianying Luo of the: NetFPGA group at Stanford University, Kevin Xie and Walkie Que of the Xilinx University Program (XUP) in China, and Defeng Li of Huawei

Hosted by Prof. Hongke Zhang

Sponsored by: Xilinx and Huawei

Date:April 23, 2008, 9am - 5pm
and April 24, 2008, 9am-Noon (follow-up session)
Location: Next Generation Internet Research Laboratory
Beijing Jiaotong University
No. 3 of Shangyuan Residence Haidian District in Beijing
No. 411 South of the No. 9 Teaching Building
Beijing, China

Abstract

An open platform called the NetFPGA has been developed at Stanford University. The NetFPGA platform enables researchers and instructors to build high-speed, hardware-accelerated networking systems. The platform can be used in the classroom to teach students how to build Ethernet switches and Internet Prototcol (IP) routers using hardware rather than software. The platform can be used by researchers to prototype advanced services for next-generation networks.

By using Field Programmable Gate Arrays (FPGAs), the NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained. During summer camp, we will use the NetFPGA to determine the amount of memory needed to buffer TCP/IP data streaming through the Gigabit/second router. Hardware circuits within the NetFPGA will be implemented to measure and plot the occupancy of buffers. Circuits will be downloaded into reconfigurable hardware and tested with live, streaming Internet video traffic.

Background

Attendees will utilize a Linux-based PC equipped with NetFPGA hardware. A basic understanding of Ethernet switching and network routing is expected. Past experience with Verilog is useful but not required. This full-day tutorial extends the material presented at the Hot Interconnects tutorial and the SIGMETRICS tutorials in 2007. Photos from those events as well as a description of the NetFPGA Platform are available on-line from the NetFPGA homepage.

Outline

  • Function of an Internet Router

    • Control plane

      • Routing protocols
      • Routing table
      • Management and Command Line Interface (CLI)

    • Datapath

      • Address lookup

        • Longest prefix match
        • Classless Interdomain Routing (CIDR)
      • Header update
      • Packet buffer

    • NetFPGA Router

      • Hardware

        • Gigabit Ethernet interfaces
        • PCI host interface
        • Field Programmable Gate Array (FPGA) Logic
        • Random Access Memory (RAM)

      • Software

        • Kernel-space driver
        • User-space applications
      • System configuration

    • Demonstration Topology

      • Hardware

        • Network of ten routers
        • Ethernet switch
        • Video server
        • High Definition (HD) video client

      • Software

        • PW-OSPF
        • Routing tables
        • Dynamic re-routing

    • Integrated Circuit Design

      • Technologies

        • Look-Up Tables (LUTs)
        • Configurable Logic Blocks (CLBs)
        • Field Programmable Gate Arrays (FPGAs)

      • Verilog Hardware Description Langauge (HDL)

        • Registers, integers, arrays
        • Multiplexers
        • Synchronous storage elements
        • Finite State Machines (FSMs)

      • Hardware Debug

        • Waveform monitor
        • In-circuit logic emulation

    • NetFPGA System Components

      • Synthesis of tutorial router

      • Java-based Graphical User Interface (GUI)

        • Configuration
        • Statistics

      • Router architecture

        • Pipeline
        • Queues

    • Buffer Size Experiment

      • Experiment with TCP/IP flows

        • Rule-of-thumb for the buffer size
        • Round-trip propation delay
        • Capacity of bottlneck link
        • Number of active flows
      • Lower delay with smaller queues

    • Enhanced Router

      • Additional hardware

        • Event capture module
        • Rate limiter
        • Delay module

      • Experiments

        • Netperf
        • HD video transport

      • Life of packet through the system

        • Description of blocks
        • Waveforms from logic analyzer

About the presentors

  • John W. Lockwood

    John W. Lockwood is a Consulting Associate Professor at Stanford University. At Stanford, he leads the NetFPGA Alpha and Beta release programs and organizes the worldwide tutorial program. Lockwood was granted tenure in the Department of Computer Science and Engineering at Washington University in Saint Louis in 2006. At Washington University in St. Louis, Lockwood led the Reconfigurable Network Group (RNG) to develop the Field programmable Port Extender (FPX) to enable rapid prototype of extensible network modules in Field Programmable Gate Array (FPGA) technology. Lockwood's research interests include reconfigurable hardware, Internet security, and content processing technologies. Dr. Lockwood earned his Ph.D from the Department of Electrical and Computer Engineering at the University of Illinois.

    John Lockwood has served as the principal investigator on grants from the National Science Foundation, Xilinx, Altera, Nortel Networks, Rockwell Collins, and Boeing. He has worked in industry for AT&T Bell Laboratories, IBM, Science Applications International Corporation (SAIC), and the National Center for Supercomputing Applications (NCSA). He served as a co-founder of Global Velocity, a networking startup company focused on high-speed data security. He is a member of IEEE, ACM, Tau Beta Pi, and Eta Kappa Nu.

  • Jianying Luo

    Jianying Luo is a PhD candidate in the Department of Electrical Engineering at Stanford University. He received his MS degree from the Department of Computing Sciences at the University of Texas at Austin. He received his BS degree from the Department of Computing Sciences at Beijing University.

  • Defeng Li

    Defeng Li is a Senior Research Engineer at Huawei Technologies, he joined Huawei in 1997 after he earned his master degree of industry automation. He worked on software development, software testing, and telecommunication standards. His research interests are in technologies issues of core routers, including consideration of optical switch fabrics and minimization of power consumption.

  • Kevin Xie

    Kevin Xie is the Xilinx University Program (XUP) manager in China.

  • Walkie Que

    Walkie Que is a student at Shanghai Jiaotong University. His interest is in microelectronics, computer architecture, and hardware design. He also works for the Xilinx University Program (XUP) in China.

Slides from the Event

Photos from the Event

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