Hot Interconnects Tutorial
Hands-on with the NetFPGA to build a Gigabit-rate Router
Presented by Nick McKeown, John W. Lockwood, Jad Naous, Glen Gibb, Adam Covington
Date: Friday, August 24, 2007
Time: 9am - 5pm
Location: Stanford University, Gates Building, Room 104.
Abstract
An open platform called the NetFPGA has been developed at Stanford University. The NetFPGA platform enables researchers and instructors to build high-speed, hardware-accelerated networking systems. The platform can be used in the classroom to teach students how to build Ethernet switches and Internet Prototcol (IP) routers using hardware rather than software. The platform can be used by researchers to prototype advanced services for next-generation networks.
By using Field Programmable Gate Arrays (FPGAs), the NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained. During summer camp, we will use the NetFPGA to determine the amount of memory needed to buffer TCP/IP data streaming through the Gigabit/second router. Hardware circuits within the NetFPGA will be implemented to measure and plot the occupancy of buffers. Circuits will be downloaded into reconfigurable hardware and tested with live, streaming Internet video traffic.
Background
Attendees will utilize a Linux-based PC equipped with NetFPGA hardware. A basic understanding of Ethernet switching and network routing is expected. Past experience with Verilog is useful but not required. This full-day tutorial extends the material presented at the half-day SIGMETRICS tutorial on June 12, 2007. Photos from that event as well as a description of the NetFPGA Platform are available on-line from the NetFPGA homepage.
Outline
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Function of an Internet Router
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Control plane
- Routing protocols
- Routing table
- Management and Command Line Interface (CLI)
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Datapath
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Address lookup
- Longest prefix match
- Classless Interdomain Routing (CIDR)
- Header update
- Packet buffer
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NetFPGA Router
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Hardware
- Gigabit Ethernet interfaces
- PCI host interface
- Field Programmable Gate Array (FPGA) Logic
- Random Access Memory (RAM)
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Software
- Kernel-space driver
- User-space applications
- System configuration
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Demonstration Topology
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Hardware
- Network of ten routers
- Ethernet switch
- Video server
- High Definition (HD) video client
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Software
- PW-OSPF
- Routing tables
- Dynamic re-routing
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Integrated Circuit Design
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Technologies
- Look-Up Tables (LUTs)
- Configurable Logic Blocks (CLBs)
- Field Programmable Gate Arrays (FPGAs)
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Verilog Hardware Description Langauge (HDL)
- Registers, integers, arrays
- Multiplexers
- Synchronous storage elements
- Finite State Machines (FSMs)
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Hardware Debug
- Waveform monitor
- In-circuit logic emulation
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NetFPGA System Components
- Synthesis of tutorial router
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Java-based Graphical User Interface (GUI)
- Configuration
- Statistics
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Router architecture
- Pipeline
- Queues
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Buffer Size Experiment
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Experiment with TCP/IP flows
- Rule-of-thumb for the buffer size
- Round-trip propation delay
- Capacity of bottlneck link
- Number of active flows
- Lower delay with smaller queues
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Enhanced Router
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Additional hardware
- Event capture module
- Rate limiter
- Delay module
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Experiments
- Netperf
- HD video transport
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Life of packet through the system
- Description of blocks
- Waveforms from logic analyzer
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About the presentors
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Nick McKeown is a Professor of Electrical Engineering and Computer Science and Faculty Director of the Clean Slate Program at Stanford University. He received his Phd from the University of California at Berkeley in 1995. From 1986-1989, he worked for Hewlett-Packard Labs in their network and communications research group in Bristol, England. During the Spring of 1995, he worked briefly for Cisco Systems where he helped architect their GSR 12000 router. In 1997 Nick co-founded Abrizio Inc., where he was CTO. Abrizio is now part of PMC-Sierra. He was co-founder and CEO of Nemo Systems, which is now part of Cisco Systems.
Nick McKeown is the STMicroelectronics Faculty Scholar, the Robert Noyce Faculty Fellow, a Fellow of the Powell Foundation and the Alfred P. Sloan Foundation, and recipient of a CAREER award from the National Science Foundation. In 2000, he received the IEEE Rice Award for the best paper in communications theory. Nick is a Fellow of the Royal Academy of Engineering (UK), and a Fellow of the IEEE and the ACM, and British Computer Society Lovelace Medal Winner, 2005. He served as an Editor for the IEEE Transactions on Communications and ACM/IEEE Transactions on Networking, and as a Guest Editor for IEEE Journal on Selected Areas on Communications, IEEE Networks Magazine and IEEE Communications Magazine, and chaired the Technical Advisory Committee for ACM Sigcomm. Nick's research interests include the architecture of the future Internet, the architecture, analysis and design of high performance switches and Internet routers, IP lookup and classification algorithms, scheduling algorithms, congestion control, routing protocols and network processors.
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John W. Lockwood is a Consulting Associate Professor at Stanford University. At Stanford, he leads the NetFPGA Alpha and Beta release programs and organizes the worldwide tutorial program. Lockwood was granted tenure in the Department of Computer Science and Engineering at Washington University in Saint Louis in 2006. At Washington University in St. Louis, Lockwood led the Reconfigurable Network Group (RNG) to develop the Field programmable Port Extender (FPX) to enable rapid prototype of extensible network modules in Field Programmable Gate Array (FPGA) technology. Lockwood's research interests include reconfigurable hardware, Internet security, and content processing technologies. Dr. Lockwood earned his Ph.D from the Department of Electrical and Computer Engineering at the University of Illinois.
John Lockwood has served as the principal investigator on grants from the National Science Foundation, Xilinx, Altera, Nortel Networks, Rockwell Collins, and Boeing. He has worked in industry for AT&T Bell Laboratories, IBM, Science Applications International Corporation (SAIC), and the National Center for Supercomputing Applications (NCSA). He served as a co-founder of Global Velocity, a networking startup company focused on high-speed data security. He is a member of IEEE, ACM, Tau Beta Pi, and Eta Kappa Nu.
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Jad Naous
Jad Naous received his B.Eng. degree in Computer Engineering from McGill University in 2005, and his M.S.E.E. degree from Stanford University in 2007. He is currently pursuing a doctorate in Electrical Engineering at Stanford University. He has previously worked as a Graduate Intern for Sun Microsystems Labs in 2006, where he worked on the next generation switch project. In 2007, he joined Agilent Technologies Labs as a Graduate Intern where he helped implement special devices for the IEEE1588 Precision Time Protocol using NetFPGA.
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Glen Gibb
Glen is a PhD candidate in Electrical Engineering at Stanford University. He received his Master of Science in Electrical Engineering from Stanford University and a Bachelor of Science and a Bachelor of Engineering from The University of Melbourne in Australia. He has been working on the NetFPGA platform since 2004 and was the lead designer for the current hardware version.
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Adam Covington
Adam Covington is a Research Associate of the High-Performance Network Group (HPN) at Stanford University. Adam is currently working on the NetFPGA project. Previously, he was a Research Associate with the Reconfigurable Network Group (RNG) at Washington University in St. Louis. Adam's research interests include reconfigurable systems, artificial intelligence (clustering and classification), and applications of artificial intelligence algorithms. Upon completing a Bachelor of Science degree in Computer Engineering in 2003, Adam earned his Masters of Science degree in Computer Science and Engineering from Washington University in December of 2006.
Presentation Slides
Video Demonstrations
Registration
Registration for the tutorial is now on-line from the link on the Hot Interconnects website. The NetFPGA tutorial is part of the Three-day Program. To attend, just click on the Registration link and select the options to register for the full conference and/or the the full-day tutorial.