NetFPGA Bangalore Tutorial

Hands-on with the NetFPGA to build a Gigabit-rate Router at Indian Institute of Science (IISc)

Presented by: John W. Lockwood and Jad Naous of the: High Performance Network Group at Stanford University and Kuruvilla Varghese of IISc.

Co-Hosted by Veena Kumar, Xilinx University Program, India.

Date: May 15-16, 2008

Time: 9am - 5pm

Location:SMDP/Micro-electronics Lab, Room No: 207
Centre For Electronics Design and Technology
Indian Institute of Science
Bangalore, India

Abstract

An open platform called the NetFPGA has been developed at Stanford University. The NetFPGA platform enables researchers and instructors to build high-speed, hardware-accelerated networking systems. The platform can be used in the classroom to teach students how to build Ethernet switches and Internet Prototcol (IP) routers using hardware rather than software. The platform can be used by researchers to prototype advanced services for next-generation networks.

By using Field Programmable Gate Arrays (FPGAs), the NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained. During the tutorial, we will use the NetFPGA to determine the amount of memory needed to buffer TCP/IP data streaming through the Gigabit/second router. Hardware circuits within the NetFPGA will be implemented to measure and plot the occupancy of buffers. Circuits will be downloaded into reconfigurable hardware and tested with live, streaming Internet video traffic.

Background

Attendees will utilize a Linux-based PC equipped with NetFPGA hardware. A basic understanding of Ethernet switching and network routing is expected. Past experience with Verilog is useful but not required. This full-day tutorial extends the material presented at the Hot Interconnects tutorial and the SIGMETRICS tutorials in 2007. Photos from those events as well as a description of the NetFPGA Platform are available on-line from the NetFPGA homepage.

Outline

  • Function of an Internet Router

    • Control plane

      • Routing protocols
      • Routing table
      • Management and Command Line Interface (CLI)

    • Datapath

      • Address lookup

        • Longest prefix match
        • Classless Interdomain Routing (CIDR)
      • Header update
      • Packet buffer

    • NetFPGA Router

      • Hardware

        • Gigabit Ethernet interfaces
        • PCI host interface
        • Field Programmable Gate Array (FPGA) Logic
        • Random Access Memory (RAM)

      • Software

        • Kernel-space driver
        • User-space applications
      • System configuration

    • Demonstration Topology

      • Hardware

        • Network of ten routers
        • Ethernet switch
        • Video server
        • High Definition (HD) video client

      • Software

        • PW-OSPF
        • Routing tables
        • Dynamic re-routing

    • Integrated Circuit Design

      • Technologies

        • Look-Up Tables (LUTs)
        • Configurable Logic Blocks (CLBs)
        • Field Programmable Gate Arrays (FPGAs)

      • Verilog Hardware Description Langauge (HDL)

        • Registers, integers, arrays
        • Multiplexers
        • Synchronous storage elements
        • Finite State Machines (FSMs)

      • Hardware Debug

        • Waveform monitor
        • In-circuit logic emulation

    • NetFPGA System Components

      • Synthesis of tutorial router

      • Java-based Graphical User Interface (GUI)

        • Configuration
        • Statistics

      • Router architecture

        • Pipeline
        • Queues

    • Buffer Size Experiment

      • Experiment with TCP/IP flows

        • Rule-of-thumb for the buffer size
        • Round-trip propation delay
        • Capacity of bottlneck link
        • Number of active flows
      • Lower delay with smaller queues

    • Enhanced Router

      • Additional hardware

        • Event capture module
        • Rate limiter
        • Delay module

      • Experiments

        • Netperf
        • HD video transport

      • Life of packet through the system

        • Description of blocks
        • Waveforms from logic analyzer

About the presentors

  • John W. Lockwood

    John W. Lockwood is a Consulting Associate Professor at Stanford University. At Stanford, he leads the NetFPGA Alpha and Beta release programs and organizes the worldwide tutorial program. Lockwood was granted tenure in the Department of Computer Science and Engineering at Washington University in Saint Louis in 2006. At Washington University in St. Louis, Lockwood led the Reconfigurable Network Group (RNG) to develop the Field programmable Port Extender (FPX) to enable rapid prototype of extensible network modules in Field Programmable Gate Array (FPGA) technology. Lockwood's research interests include reconfigurable hardware, Internet security, and content processing technologies. Dr. Lockwood earned his Ph.D from the Department of Electrical and Computer Engineering at the University of Illinois.

    John Lockwood has served as the principal investigator on grants from the National Science Foundation, Xilinx, Altera, Nortel Networks, Rockwell Collins, and Boeing. He has worked in industry for AT&T Bell Laboratories, IBM, Science Applications International Corporation (SAIC), and the National Center for Supercomputing Applications (NCSA). He served as a co-founder of Global Velocity, a networking startup company focused on high-speed data security. He is a member of IEEE, ACM, Tau Beta Pi, and Eta Kappa Nu.

  • Kuruvilla Varghese

    Kuruvilla Varghese is a Principal Research Scientist at Centre for Electronics Design and Technology (CEDT), Indian Institute of Scinece, Bangalore. He is working in communications network group of CEDT. His main reserach interests are in Embedded systems, Communication networks and Digital VLSI systems. Presently he is working on High performance netwoking functions using Field Programmable Gate Arrays (FPGA).

  • Jad Naous

    Jad Naous received his B.Eng. degree in Computer Engineering from McGill University in 2005, and his M.S.E.E. degree from Stanford University in 2007. He is currently pursuing a doctorate in Electrical Engineering at Stanford University. He has previously worked as a Graduate Intern for Sun Microsystems Labs in 2006, where he worked on the next generation switch project. In 2007, he joined Agilent Technologies Labs as a Graduate Intern where he helped implement special devices for the IEEE1588 Precision Time Protocol using NetFPGA.

Map

IISc Map

To Attend this Event

To Register to attend, Submit a registration form on-line.

Accomodations: Hoysala Guest House, IISc

Presentation Slides

Photos from the Event