Abstract

By using Field Programmable Gate Arrays (FPGAs), the NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained. During the tutorial, we will use the NetFPGA to determine the amount of memory needed to buffer TCP/IP data streaming through the Gigabit/second router. Hardware circuits within the NetFPGA will be implemented to measure and plot the occupancy of buffers. Circuits will be downloaded into reconfigurable hardware and tested with live, streaming Internet video traffic.

This full-day hands-on tutorial will be held in a classroom or laboratory equipped with ten PCs with NetFPGA hardware on Sunday or Monday, August 17 or 18, 2008.

Background

Outline

• Introduction to the operation of an Internet Router
  • Control plane
    • Routing protocols
    • Routing table
    • Management interfaces
  • Datapath
    • Longest Prefix Match (LPM)
    • Classless Interdomain Routing (CIDR)
    • Header processing
    • Packet buffering

• The NetFPGA Router
  • Hardware
    • Gigabit Ethernet interfaces
    • Field Programmable Gate Array (FPGA) Logic
    • Random Access Memory (RAM)
  • Software
    • Kernel-space driver
    • User-space applications
    • PCI host interface
  • System configuration

• Demonstration Topology
  • Hardware
    • Network of ten routers
    • Ethernet switch
    • Video server
    • High Definition (HD) video client
  • Software
    • PW-OSPF
    • Routing tables
    • Dynamic re-routing

• Integrated Circuit Design
  • Technologies
    • Look-Up Tables (LUTs)
    • Configurable Logic Blocks (CLBs)
    • Field Programmable Gate Arrays (FPGAs)
  • Verilog Hardware Description Langauge (HDL)
    • Registers, integers, arrays
    • Multiplexers
    • Synchronous storage elements
    • Finite State Machines (FSMs)
  • Hardware Debug
    • Waveform monitor
    • In-circuit logic emulation

• NetFPGA System Components
  • Synthesis of tutorial router
  • Java-based Graphical User Interface (GUI)
    • Configuration
    • Statistics
  • Router architecture
    • Pipeline
    • Queues

• Buffer Size Experiment
  • Experiment with TCP/IP flows
    • Rule-of-thumb for the buffer size
    • Round-trip propation delay
    • Capacity of bottlneck link
    • Number of active flows
  • Lower delay with smaller queues

• Enhanced Router
  • Additional hardware
    • Event capture module
    • Rate limiter
    • Delay module
  • Experiments
    • Netperf
    • HD video transport
  • Life of packet through the system
    • Description of blocks
    • Waveforms from logic analyzer

About the presentors

• John W. Lockwood
  John W. Lockwood is a Consulting Associate Professor at Stanford University. At Stanford, he leads the NetFPGA Alpha and Beta release programs and organizes the worldwide tutorial program. Lockwood was granted tenure in the Department of Computer Science and Engineering at Washington University in Saint Louis in 2006. At Washington University in St. Louis, Lockwood led the Reconfigurable Network Group (RNG) to develop the Field programmable Port Extender (FPX) to enable rapid prototype of extensible network modules in Field Programmable Gate Array (FPGA) technology. Lockwood's research interests include reconfigurable hardware, Internet security, and content processing technologies. Dr. Lockwood earned his Ph.D from the Department of Electrical and Computer Engineering at the University of Illinois.

  John Lockwood has served as the principal investigator on grants from the National Science Foundation, Xilinx, Altera, Nortel Networks, Rockwell Collins, and Boeing. He has worked in industry for AT&T Bell Laboratories, IBM, Science Applications International Corporation (SAIC), and the National Center for Supercomputing Applications (NCSA). He served as a co-founder of Global Velocity, a networking startup company focused on high-speed data security. He is a member of IEEE, ACM, Tau Beta Pi, and Eta Kappa Nu.

• Glen Gibb
  Glen is a PhD candidate in Electrical Engineering at Stanford University. He received his Master of Science in Electrical Engineering from Stanford University and a Bachelor of Science and a Bachelor of Engineering from The University of Melbourne in Australia. He has been working on the NetFPGA platform since 2004 and was the lead designer for the current hardware version.

• Adam Covington
  Adam Covington is a Research Associate of the High-Performance Network Group (HPN) at Stanford University. Adam is currently working on the NetFPGA project. Previously, he was a Research Associate with the Reconfigurable Network Group (RNG) at Washington University in St. Louis. Adam's research interests include reconfigurable systems, artificial intelligence (clustering and classification), and applications of artificial intelligence algorithms. Upon completing a Bachelor of Science degree in Computer Engineering in 2003, Adam earned his Masters of Science degree in Computer Science and Engineering from Washington University in December of 2006.

Schedule

To Register

• Register directly with SIGCOMM to attend the confernece and/or the NetFPGA workshop.