NetFPGA Summer Camp 2010

Build an Internet routers and learn about clean-slate switches at a 5-day summer camp held at Stanford University

Open to: Academics teaching classes with the NetFPGA, and researchers (postdoc or graduate-student) interested in developing new hardware-accelerated network applications.

Location: The Stanford University campus located between San Francisco and San Jose in the heart of Silicon Valley.

Dates: Monday, August 9 - Friday, August 13, 2010, Time: 9am - 5pm. Evening events will be announced here.

Presented by: the Stanford NetFPGA Group.

Abstract

An open platform called the NetFPGA has been developed at Stanford University. The NetFPGA platform enables researchers and instructors to build high-speed, hardware-accelerated networking systems. The platform can be used in the classroom to teach students how to build Ethernet switches and Internet Prototcol (IP) routers using hardware rather than software. The platform can be used by researchers to prototype advanced services for next-generation networks.

By using Field Programmable Gate Arrays (FPGAs), the NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained. During the tutorial, we will use the NetFPGA to determine the amount of memory needed to buffer TCP/IP data streaming through the Gigabit/second router. Hardware circuits within the NetFPGA will be implemented to measure and plot the occupancy of buffers. Circuits will be downloaded into reconfigurable hardware and tested with live, streaming Internet video traffic.

Background

Attendees will utilize a Linux-based PC equipped with NetFPGA hardware. A basic understanding of Ethernet switching and network routing is expected. Past experience with Verilog is useful but not required. This week-long summercamp extends the material presented at the shorter workshop events.

Outline

Day 1 (Monday, Aug. 9)

Welcome and introductions
Day 1
- Background
  - Basics of an IP Router
  - The NetFPGA hardware
  - How people use the NetFPGA
  - Why people use the NetFPGA
- The Stanford Base Reference Router
  - Inside the NetFPGA hardware
  - Introduction to FPGAs and Verilog
- The Enhanced Reference Router
  - Buffer sizing requirements in a router
  - Observering and controlling the queue size
- Life of a packet through the NetFPGA
  - Data and control planes
  - Interface to software: Exceptions and Host I/O
- Demonstration of the NetFPGA
  - Address Lookup
  - PW-OSPF
  - Java-based Graphical User Interface (GUI)
  - Demonstration of High Definition (HD) video streaming
- Slides: Will be available here
Dinner: To be announced

Day 2 (Tuesday, Aug. 17)

Module Development and Testing
- Running ModelSim with the NetFPGA TestBench
  - Compile, simulate, view waveforms
  - Example: Simply Encryption on a packet payload
  - Scrambling the payload with XOR using a key from a register
- Regression testing to verify hardware functionality
  - Synthesize and run the hardware
  - Verify value: 0xFFFFFFFF (would invert every bit of every byte of payload)
  - Verify value: 0xFF00FF00 (would invert every other byte of payload)
  - Verify value: 0x55555555 (would invert every other bit of payload)
- Slides: Will be available here
Introduction to OpenFlow
- Show how to use and test OpenFlow
- Describe implementation of OpenFlow
- Show use OpenFlow LiveCD
- Give example of LiveCD on nf-test machines
- Slides: Will be available here
Dinner: To be announced

Day 3 (Wednesday, Aug. 18)

Group discussion
- Projects ideas
- Scope of work that can be accomplished in 2-3 days
Team up for Projects
- Project leaders will describe projects
- Group will provide feedback on the scope
- Be sure to have one hardware designer per team
Example Hardware Design
- Background and review of block diagrams
- Show design running on nf-test machines
- Discuss relevent Verilog Code

Day 4 (Thursday, Aug. 12)

Work on Projects, examples from Summerschool 2010
- 802.1q VLANs
- Hardware-Accelerated Mathematics Library for NetFPGA
- MACinMAC
- Heavy Hitter Identification using Multistage filters
- Layer 2 Load Balancing
- Pattern Matching/Mini-IDS
- TCP Traffic Analysis for Passive End-to-End Bandwidth Measurement
- Assessment of Prototyping an AFDX Policy Switch Leveraging NetFPGA, Ethane, and OpenFlow Switch
- ntop on NetFPGA
- Universal Hash Function
NetFPGA group available for Questions and Answers

Day 5 (Friday, Aug. 13)

Complete Projects
10-minute project presentations.
Live demonstrations
Award prizes to winning projects
Dinner: To be announced

Saturday, Aug 14

Checkout of Stanford Guest House

Background Reading

To Attend this Event

Mark your calendar with the dates of the event
- Please plan to arrive Sunday night, August 8
- Please plan to stay through Saturday morning, August 14
- Registration fee covers shared meals (all breakfasts, lunches, and most dinners)
  - Registration Fee: TBD
  - Register: (registeration page coming!)
- A limited number of scholarships are available for students or instructors from schools unable to cover registration and hotel expenses.
  - Award of the scholarships will be based on both merit and need:
  - Please provide one paragraph about that describes your relevant technical background in networking and/or hardware design.
  - Please provide another paragraph that explains why you or your host institution needs financial help.
Travel Information
- Direct flights are available to most parts of the country through SFO or SJC
- CalTrain offers fast transportation between the airports and Palo Alto
- The Marguerite Shuttle offers rides between the train station, hotel, and campus. No car rental is needed.
Book accomodations at the Stanford Guest House.
- Single rooms are (price being determined)
- Shuttle service available to campus