NetFPGA-10G Information

Release Note - March 15th, 2012

We are proud to announce the Beta program is now open for the 4x10GE version of NetFPGA: The NetFPGA-10G!

The Beta programme is open and once you have registered, as explained on the Going Beta page, you will be able to download the code base as a git repository from the NetFPGA GitHub site.


The NetFPGA-10G board was designed by the NetFPGA team and is available from HTG. It has 4 x 10GigE SFP+ interfaces, a PCI Express interface to the host (Gen2 x8 channels), and a Xilinx Virtex-5 TX240T FPGA. The board has SRAM and DRAM (27 MBytes QDRII SRAM, 288 MBytes RLDRAM-II) and a high bandwidth expansion connector for daughter-cards. Further technical details on the board, along with purchasing information, can be found at HTG’s website here. You can see a photo of the board at or below.


The Academic price is $1,675.

Code Base:

This first release comes with a modest (but steadily growing) code base of hardware and software to get you started. The design flow is based on EDK and AXI. Once you have registered on github and NetFPGA-live successfully, you will have access to all platform documentation at NetFPGA-10G Github wiki and Getting-Started-Guide. The latter explains how to download the code base as either a tarball or a git repository from the NetFPGA GitHub site. Please make sure you are logged into github to access NetFPGA-10G Github wiki and Getting-Started-Guide else you will get a 404 error from github.
We hope you enjoy the new platform and we look forward to your feedback, comments, and discussion on the mailing list. It is a pleasure and honor to work with the whole NetFPGA community, and we look forward to working with you in 2012. Together, let’s develop great new open-source networking hardware! Let’s enable great teaching and research in networking hardware! We will update you as we prepare for major new releases of the code base in the coming months. Stay tuned!
Hardware Features

  • Xilinx Virtex-5 XC5VTX240TFFG1759 -2
  • Four SFP+ interface (using 16 RocketIO GTX transceivers and 4 PHY devices)
  • Supports both 10Gbps and 1Gbps modes
  • X8 PCI Express Gen 2 (5Gbps/lane)
  • Twenty Configurable GTX Serial Transceivers (available through two high-speed Samtec connectors)
  • Three x36 QDR II (CY7C1515KV18)
  • Four x32 RLDRAM II (MT49H16M36BM-25)
  • Mictor Connector for debugging
  • Two Platform XL Flash (128mb each)
  • One Xilinx XC2C256 CPLD
  • One DB9 (RS232)
  • User LEDs & Push Buttons
  • 9.5” x 4.25” board size


FPGA Design

The current NetFPGA infrastructure release comes with reference designs that operate the NetFPGA-10G as a NIC in 1G or 10G mode with all 4 ports active. In addition, the release provides the basic building blocks of all future designs, including and PCIe endpoint with DMA, as well as software. A board self-test suite is also included.

More Information

For more information, visit NetFPGA website for the latest update -, or if you haven’t already, sign up to netfpga-announce mailing list

Core Developers

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