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10G Platform Project Table
TopReference Projects
Project Title | Organization | Documentation |
---|---|---|
Production Test | Stanford University | Wiki |
RLDRAM Test | Xilinx | Wiki |
10G Ethernet Interface Loopback Test | Stanford University / University of Cambridge | Wiki |
1G Ethernet Interface Loopback Test | Stanford University / University of Cambridge | Wiki |
Reference NIC 10G | Stanford University / University of Cambridge | Wiki |
Reference NIC 1G | Stanford University / University of Cambridge | Wiki |
Flash Configuration | University of Cambridge | Wiki |
Learning CAM Switch | University of Pisa / University of Cambridge | Wiki |
Contributed Projects
Project Title | Organization | Documentation |
---|---|---|
NetFPGA-1G Ported Switch 10G | University of Pisa / University of Cambridge | Wiki |
NetFPGA-1G Ported NIC 1G | University of Pisa / University of Cambridge | Wiki |
NIC | Stanford University / University of Cambridge | Wiki |
OpenFlow Switch | Stanford University | Wiki |
NIC (SRAM) | Stanford University / University of Cambridge | Wiki |
Simple 10G Switch | Xilinx | Wiki |
NetFlow simple 10G Bram | Universidad Autónoma de Madrid | Wiki |
Flash | University of Cambridge | Wiki |
1G Platform Project Table
TopProject Title | Base Version |
Status | Organization | Documentation |
---|---|---|---|---|
IPv4 Reference Router | 2.1.1 | Functional | Stanford University | Guide |
Quad-Port Gigabit NIC | 2.1.1 | Functional | Stanford University | Guide |
Ethernet Switch | 2.1.1 | Functional | Stanford University | Wiki |
Buffer Monitoring System | 2.1.1 | Functional | Stanford University | Guide |
Hardware-Accelerated Linux Router | 2.1.1 | Functional | Stanford University | Guide |
DRAM-Router | 2.1.1 | Functional | Stanford University | Wiki |
DRAM-Queue Test | 2.1.1 | Functional | Stanford University | Wiki |
Packet Generator | 2.1.1 | Functional | Stanford University | Wiki |
OpenFlow Switch | 2.2.0 | Functional | Stanford University | Wiki |
NetFlow Probe | 1.2 | Functional | Brno University | Wiki |
AirFPGA | 2.0 | Functional | Stanford University | Wiki and Paper |
Fast Reroute & Multipath Router | 2.0 | Functional | Stanford University | Wiki |
NetThreads | 1.2.5 | Functional | University of Toronto | Wiki |
NetThreads-RE | 2.0 | Functional | University of Toronto | Wiki |
NetTM | 2.0 | Functional | University of Toronto | Wiki |
Precise Traffic Generator | 1.2.5 | Functional | University of Toronto | Wiki |
URL Extraction | 2.0 | Functional | Univ. of New South Wales | Wiki |
zFilter Sprouter (Pub/Sub) | 1.2 | Functional | Ericsson | Wiki |
Windows Driver | 2.0 | Functional | Microsoft Research | Wiki |
RED | 2.0 | Functional | Stanford University | Wiki |
Open Network Lab | 2.0 | Functional | Washington University | Wiki |
DFA | 2.0 | Functional | UMass Lowell | Wiki |
G/PaX | ?.? | Functional | Xilinx | Wiki |
RCP Router | 2.0 | Functional | Stanford University | Wiki |
Deficit Round Robin (DRR) | 2.0 | Functional | Stanford University | Wiki |
OpenFlow-MPLS Switch | 2.0 | Functional | Ericsson | Wiki |
PTP-enabled Router | 2.0 | Functional | Stanford University | Wiki |
Vlan Tag Handler | 2.1.1 | Functional | Stanford University | Wiki |
Port Aggregator | 2.0 | Functional | Stanford University | Wiki |
IP Lookup w/Blooming Tree | 1.2.5 | In Progress | University of Pisa | Wiki |
KOREN Testbed | ?.? | In Progress | Chungnam-Korea | Wiki |
Virtual Data Plane | 1.2 | In Progress | Georgia Tech | Wiki |
Deficit Round Robin (DRR) Input Arbiter | 1.2 | In Progress | Universidade Federal do Rio Grande do Sul (Brazil) | Wiki |
Counter Braids | 2.0 | Functional | Stanford (Lu, Jianying) | Wiki |
Ethernet Switch with Real-time support |
2.0 | Functional | University of Waterloo and Universidad de Concepcion | Wiki |
End-to-End Ethernet Authorization | 2.0 | In Progress | Euskal Herriko Unibertsitateko | Wiki |
Ultra-high Speed Congestion-control | 2.0 | In Progress | University of North Carolina | Wiki |
Promiscuous Reference Router | 2.0 | Functional | University of Catania | Wiki |
BORPH (Operating System) | 2.1.1 | Functional | University of Hong Kong / University of Cape Town | Wiki |
Traffic Monitor | 2.0 | Functional | University of Catania | Wiki |
Latency Measurement Module | 1.0 | Functional | Algo-Logic Systems | Wiki |
NetFPGA Logic Analyzer | 2.0 | Functional | USC/ISI | Wiki |
Bounded Jitter Policy | 2.0 | Functional | University of Toronto | Wiki |
Traffic Classifier | 2.0 | Functional | University of Toronto | Wiki |
Network IO Fairness | 2.0 | Functional | Georgia Tech | Wiki |
Tunneling OpenFlow Switch with ICMP | 2.0 | Functional | Stanford University | Wiki |
zFormation PSrouter (Pub/Sub) | 2.0 | Functional | Ericsson | Wiki |
High Performance Packet Classifier | 2.0 | Functional | University of Pisa | Wiki |
Flexible Router | 2.0 | Functional | University of Catania | Wiki |
Monitoring System | 2.1 | Functional | University of Pisa/University of Cambridge | Wiki |
Deficit Round Robin Router Backplane | 2.2 | In Progress | Cairo University | Wiki |
NetCoding Project Transmit Node | 2.1 | Functional | ? | Download |
Router Buffer Adaptation | 2.2.0 | Functional |
University of New South Wales | Wiki |