IETF Tutorial 2010 (Anaheim)

Hands-on with the NetFPGA to build a Gigabit-rate Router

Presented by: G. Adam Covington, James Zheng of the High Performance Network Group at Stanford University

Date: Sunday, March 21, 2010

Time: 9am - 5pm

Location: Manhattan Room, Anaheim Hilton, Anaheim, California, United States


An open platform called the NetFPGA has been developed at Stanford University. The NetFPGA platform enables researchers and instructors to build high-speed, hardware-accelerated networking systems. The platform can be used in the classroom to teach students how to build Ethernet switches and Internet Prototcol (IP) routers using hardware rather than software. The platform can be used by researchers to prototype advanced services for next-generation networks.

By using Field Programmable Gate Arrays (FPGAs), the NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained. During the tutorial, we will use the NetFPGA to determine the amount of memory needed to buffer TCP/IP data streaming through the Gigabit/second router. Hardware circuits within the NetFPGA will be implemented to measure and plot the occupancy of buffers. Circuits will be downloaded into reconfigurable hardware and tested with live, streaming Internet video traffic.

This full-day hands-on tutorial will be held in a classroom or laboratory equipped with ten PCs with NetFPGA hardware on Sunday, March 21, 2010.


Attendees will utilize a Linux-based PC equipped with NetFPGA hardware. A basic understanding of Ethernet switching and network routing is expected. Past experience with Verilog is useful but not required. This full-day tutorial extends the material presented at previous NetFPGA Turorials from 2007-2009 (FPL 2009, SIGCOMM 2008, Hot Interconnects 2007, SIGMETRICS 2007). Information about previous events as well as a description of the NetFPGA Platform are available on-line from the NetFPGA homepage.


  • Introduction to the operation of an Internet Router
    • Control Plane
      • Routing protocols
      • Routing table
      • Management interfaces
    • Datapath
      • Longest Prefix Match (LPM)
      • Classless Interdomain Routing (CIDR)
      • Header processing
      • Packet buffering
  • The NetFPGA Router
    • Hardware
      • Gigabit Ethernet interfaces
      • Field Programmable Gate Array (FPGA) Logic
      • Random Access Memory
    • Software
      • Kernel-space driver
      • User-space applications
      • PCI host interface
    • System Configuration
  • Demonstration Topology
    • Hardware
      • Network of ten routers
      • Ethernet switch
      • Video server
      • High Definition (HD) video client
    • Software
      • PW-OSPF
      • Routing tables
      • Dynamic re-routing
  • Integrated Circuit Design
    • Technologies
      • Look-Up Tables (LUTs)
      • Configurable Logic Blocks (CLBs)
      • Field Programmable Gate Arrays (FPGAs)
    • Verilog Hardware Description Language (HDL)
      • Registers, integers, arrays
      • Multiplexer
      • Synchronous storage elements
      • Finite State Machines (FSMs)
    • Hardware Debug
      • Waveform monitor
      • In-circuit logic emulation
  • NetFPGA System Components
    • Synthesis of tutorial router
    • Java-based Graphical User Interface
      • Configuration
      • Statistics
    • Router Architecture
      • Pipeline
      • Queues
  • Buffer Size Experiment
    • Experiment with TCP/IP
      • Rule-of-thumb for the buffer size
      • Round-trip propation delay
      • Capacity of bottlneck link
    • Lower delay with smaller queues
  • Enhanced Router
    • Additional hardware
      • Event capture module
      • Rate limiter
      • Delay module
    • Experiments
      • Netperf
      • HD video transport
    • Life of packet through the system
      • Description of blocks
      • Waveforms from logic anazlyzer

About the presentors

  • Adam Covington
    Adam is a Research Associate of the High-Performance Network Group (HPN) at Stanford University. He is currently working on the NetFPGA project, which enables researchers and instructors to build hardware-accelerated networking systems. Previously, he was a Research Associate with the Reconfigurable Network Group (RNG) at Washington University in St. Louis. While at Washington University he designed, and implemented clustering algorithms on FPGAs and supported a hardware accelerated classification system on the FPX platform. Adam’s current research interests include reconfigurable systems, artificial intelligence (clustering and classification), and applications of artificial intelligence algorithms. Adam completed a Bachelor of Science degree in Computer Engineering from Western Michigan University in April 2003 and accepted a Distinguished Masters of Science Fellowship from Washington University. He completed his Masters of Science degree in Computer Science and Engineering from Washington University in December 2006. Adam continues to provide support for the NetFPGA project which includes helping users worldwide as well as arranging and presenting tutorials.

  • James Hongyi Zeng
    James Hongyi Zeng received his Bachelor of Science degree in Electrical Engineering from Tsinghua University, China in 2008, with a concentration in wireless communication. He is currently pursuing a PhD degree in Electrical Engineering at Stanford University. His research mainly focuses on data center network, high performance router architecture, and software defined radio. He has been working on the NetFPGA platform since 2008 and is the core designer on the next generation NetFPGA 10G platform. James has previously worked in Microsoft Research Asia as a Visiting Student, where he worked on GPU-based soft WiFi project.

9:00-10:30 Tutorial Session
10:30-11:00 Coffee Break
11:00-12:30 Tutorial Session
12:30-1:30 Lunch
1:30-3:00 Tutorial Session
3:00-3:30 Coffee Break
4:00-5:30 Tutorial Session


Cost of the tutorial is $200. Register here to attend