NetFPGA PLUS Release 1.0.0

Posted: 24 September 2021

It is with great excitement we announce the release of NetFPGA PLUS.

NetFPGA PLUS 1.0.0

NetFPGA PLUS 1.0.0 has arrived, available in a public repository to all, links on the netfpga.org website. I’ve reprinted the outline, included as part of the original announcement, at the bottom of this newsletter. The overly optimistic timetable fell to the brutal realities of the last 9 months.

NetFPGA PLUS has been is a momentous effort that largely has fallen to the broad shoulders of the increasingly slim NetFPGA team at Cambridge; one person in particular deserves much credit for this huge effort and for us achieving this first release.

On behalf of us all, I thank Yuta Tokusashi who has lead the NetFPGA PLUS work throughout this effort and who has managed this despite the extraordinary challenges of the last 18 months.

Many critical issues were managed and overcome with the expert guidance of Noa Zilberman, while release testing and preparation would not have been possible without the assistance of Salvator Galea.

This entire effort was enabled by many members of the excellent Xilinx team from Gordon Brebner’s leadership and enthusiasm through to the phenomenal efforts of the Open-NIC team; notably Yan Zhang, and Chris Neely, as well as critical advice from Cathal McCabe, part of Xilinx in Dublin.

My personal thanks and on behalf of the NetFPGA community to each of them. (I’m excruciatingly aware the moment I send this email I will realise I’ve not credited a critical member of the team - my apologies in advance.)

I will leave some details to a future newsletter - in preparation - but promise it shortly, as soon as we have all caught up on our sleep.

Do check out the new website, thanks to Adam Pettigrew for his efforts there; and of course do check out the public, openly available, Apache licensed, NetFPGA PLUS codebase too!

Items planned for the next announcement will include

1. License change for NetFPGA
2. NetFPGA PLUS plans
3. NetFPGA SUME status

Thank you all, Andrew Moore on behalf of the NetFPGA team.

NetFPGA SUME Release 1.10.0

Posted: 2 October 2020

Greetings NetFPGA community, We are pleased to announce today the next release (1.10.0) of the NetFPGA-SUME code base. This release includes:

Reference projects:

• all reference projects and reference cores have been migrated to Vivado 2020.1, Ubuntu 2020.4 LTS and Python 3,
• new standard core: nic_output_queues - this core is based on the output queue ip core and enables a backpressure to the output port lookup,
• fix in 10g attachment unit core in TX queue: this enables more efficient version of TX queue and allows to handle deficit idle count (fix from P4-NetFPGA project),
• reference_nic project has a backpressure enabled in the output queues.

Contrib Projects:

• corundum: ports of verilog-pcie, verilog-ehternet, and corundum projects to NetFPGA SUME board.

Driver:

• new SUME riffa driver for FreeBSD.

If you have not registered to the NetFPGA-SUME beta program, you will need to do so to access the repository: Registration Form

You can find more information about NetFPGA-SUME code base in the NetFPGA-SUME wiki

More information about the release: Release-Notes

We invite everyone from the community to use and improve our repository, and hope to see a lot of projects contributed to the repository.

Kind Regards,

The NetFPGA team

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NetFPGA project wins SOSR System Award

Posted: 2 April 2019

Greetings NetFPGA community,

We are pleased to announce that the NetFPGA project was awarded today the ACM SIGCOMM SOSR System Award.

The NetFPGA is an open platform enabling researchers and students to build high-speed, hardware-accelerated networking systems. The platform is used by researchers to prototype advanced services for next-generation networks. It is also used in the classroom to teach students how to build network devices, such as Ethernet switches and Internet Protocol (IP) routers. The platform combines both hardware (boards) and software (embedded, tools and applications), together with reference designs and community contributed projects.

Originally developed for teaching at Stanford in 2002 and becoming widely available in 2003, NetFPGA has developed a large community of over 1200 users, using more than 3500 cards, at over 300 universities, in over 60 countries across 6 continents. Alongside supporting academic teaching and research, NetFPGA sees use and contributions from professional research community with over 50 active corporate-based contributors.

The prominent early success of NetFPGA has been its contribution to OpenFlow, which in turn reignited the Software Defined Networking movement. By providing a widely available open-source OpenFlow development platform capable of line-rate operation, NetFPGA was, until commercial uptake, the reference hardware platform for OpenFlow.

In recent years, NetFPGA was increasingly used for the prototyping of programmable data planes, and it currently offers the only open-source hardware target for P4 programs (previously through P4FPGA, and nowadays using the P4->NetFPGA framework).

NetFPGA has been used for the implementation of over 500 research projects, and to date has been referenced in over three thousand publications.

The NetFPGA project is academically led by the Universities of Cambridge and Stanford, supported by generous donations from Xilinx, Micron, Cypress and Linear Technologies and generous support from the National Science Foundation, DARPA, the Research Council UK through the Engineering and Physical Sciences Council, and the European Union’s Horizon 2020 research and innovation programme.

“The CTO Office at Xilinx has been involved in the open source NetFPGA project since its inception. In particular, the Xilinx University Program has ensured that the NetFPGA family – featuring multiple generations of Xilinx FPGAs over the years – has been successfully used by academic researchers and teachers. Xilinx Labs has also had direct technical involvements, ranging from NetFPGA board and shell design on the hardware side, to P4→NetFPGA tool flow development on the software side. Xilinx is very happy to see this well-deserved award, which reflects the great impact of NetFPGA worldwide on research and teaching using FPGA-based software-defined networking.” - Gordon Brebner, Distinguished Engineer, Xilinx Labs

“Cypress is pleased to continue its support for the NetFPGA project and its valuable training and research work in areas including Cyber Security at the Edge and in the Cloud,” said Patrick Kane, director of the Cypress University Alliance, Cypress. “Our relationship with the NetFPGA has spanned over 12 years and has included providing world-class Cypress semiconductor solutions for all versions of the NetFPGA platform.”

NetFPGA SUME Release 1.9.0

Posted: 1 April 2019

Greetings NetFPGA community,

We are pleased to announce today the next patch release (1.9.0) of the NetFPGA-SUME code base.

This release includes:

Bug Fix:

• nf_axis_converter_v1_0_0: Fix timing issue on the path between the nf_axis_converter and the tx_queue. The timing issue was causing the nf_axis_converter output to be incorrect, which in turn caused the MAC to reject packets of certain lengths. Added an AXIS pipeline stage on the output of the nf_axis_converter

Contrb Projects:

• lake: Layered Key-value store, a hardware-based implementation of memcached server
• reference_emu_dns: Implementation of a DNS server with the Emu framework and integrated into the SUME reference data path
• nic_v2: Reference NIC with the new DMA engine core

Contrib Cores:

• db_v1_0_1: A key-value cache which stores key-value pair on DRAM and BRAM
• div_v1_0_0: A packet distributer, based on UDP port number and this module acts as in-network computing on-demand controller
• emudns_output_port_lookup_v1_0_0: Output port lookup core generated by the Emu framework with DNS functionality
• input_arbiter_6in_v1_0_0: Provides support for an additional internal high-priority 50Gbps queue
• nf_naudit_dma_v1_0_0: New DMA engine
• nf_sume_pktgen_v1_0_0: Enables internal packet injection at full speed (~50Gbps)

If you have not registered to the NetFPGA-SUME beta program, you will need to do so to access the repository: Registration Form

You can find more information about NetFPGA-SUME code base in the NetFPGA-SUME wiki

More information about the release: Release-Notes

We invite everyone from the community to use and improve our repository, and hope to see a lot of projects contributed to the repository.

Kind Regards,

The NetFPGA team

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NetFPGA SUME Release 1.8.0

Posted: 30 January 2018

Greetings NetFPGA community,

We are pleased to announce today the next patch release (1.8.0) of the NetFPGA-SUME code base.

This release includes:

Fix for manual test via uart not working:

• Using UART to run manual test did not work previously for reference_switch and reference_switch_lite. This has been fixed

Fix for acceptance test crash in headless mode:

• NfSumeTest.py is run during acceptance test. This script assumed the presence of a display which caused a crash. The fix now allows the script to be run without a display.

New contribution - script to generate the regs_gen.py file:

• The new file csv_gen.py can be used instead of running the excel macro inside module_generation.xlsm.

If you have not registered to the NetFPGA-SUME beta program, you will need to do so to access the repository: Registration Form

You can find more information about NetFPGA-SUME code base in the NetFPGA-SUME wiki

More information about the release: Release-Notes

We invite everyone from the community to use and improve our repository, and hope to see a lot of projects contributed to the repository.

Kind Regards,

The NetFPGA team

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NetFPGA SUME Release 1.7.1

Posted: 14 December 2017

Greetings NetFPGA community,

We are pleased to announce today the next patch release (1.7.1) of the NetFPGA-SUME code base.

This release includes:

Hotfix:

• Corenf_10ge_interface_v1_0_0 : Disabled deficit idle count on TX MAC in 10G ports as enabling it causes packet drop under some scenarios.

If you have not registered to the NetFPGA-SUME beta program, you will need to do so to access the repository: Registration Form

You can find more information about NetFPGA-SUME code base in the NetFPGA-SUME wiki

More information about the release: Release-Notes

We invite everyone from the community to use and improve our repository, and hope to see a lot of projects contributed to the repository.

Kind Regards,

The NetFPGA team

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NetFPGA SUME Release 1.7.0

Posted: 13 October 2017

Greetings NetFPGA community,

We are pleased to announce today the next patch release (1.7.0) of the NetFPGA-SUME code base.

This release includes:

Update:

• Ubuntu 16.04 – Operating System Setup Guide (wiki-page) has been updated

Cores:

• nf_10ge_interface_v1_0_0 : Enabled deficit idle count on TX MAC in 10G ports
• barrier_v1_0_0 : move the inactivity timeout inside barrier definition

Contrib Projects:

• reference_switch_lcam : increase CAM size 982 to 1024 entries

If you have not registered to the NetFPGA-SUME beta program, you will need to do so to access the repository: Registration Form

You can find more information about NetFPGA-SUME code base in the NetFPGA-SUME wiki

More information about the release: Release-Notes

We invite everyone from the community to use and improve our repository, and hope to see a lot of projects contributed to the repository.

Kind Regards,

The NetFPGA team

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NetFPGA SUME Release 1.6.1

Posted: 3 August 2017

Greetings NetFPGA community,

We are pleased to announce today the next patch release (1.6.1) of the NetFPGA-SUME code base.

This release includes: Hot Fix:

• switch_output_port_lookup_v1_0_1 : Fix tuser handling in reference_switch output port lookup
• router_output_port_lookup_v1_0_0 : Fix the OPL of the reference_router to handle the backpresure and tuser of the modified OQs
• output_queues_v1_0_0 : Fix output queues handling of tuser + changed AXI-S bus to behave as in other modules

If you have not registered to the NetFPGA-SUME beta program, you will need to do so to access the repository: Registration Form

You can find more information about NetFPGA-SUME code base in the NetFPGA-SUME wiki

More information about the release: Release-Notes

We invite everyone from the community to use and improve our repository, and hope to see a lot of projects contributed to the repository.

Kind Regards,

The NetFPGA team

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NetFPGA SUME Release 1.6.0

Posted: 13 July 2017

Greetings NetFPGA community,

We are pleased to announce today the next minor release (1.6.0) of the NetFPGA-SUME code base.

This release includes:

Updates:

• Xilinx Core
  • cam_v1_1_0 : Change CAM type to BRAM to improve timing
• Projects
  • reference_nic : Migrate to Vivado v2016.4
  • reference_switch : Migrate to Vivado v2016.4
  • reference_switch_lite : Migrate to Vivado v2016.4
  • reference_router : Migrate to Vivado v2016.4
  • acceptance_test : Migrate to Vivado v2016.4

Bug Fix

• switch_output_port_lookup_v1_0_1 : Fix tuser signal handling
• output_queues_v1_0_0 : Fix output queues handling of tuser
• cam_v1_1_0 : Fix ternary mode

Contrib Projects:

• encap_decap : encap/decap VLAN tag
• reference_switch_lcam : reference_switch with large CAM

Contrib Cores:

• vlan_adder_v1_0_0 : used in encap_decap contrib-project
• vlan_remover_v1_0_0 : used in encap_decap contrib-project
• nic_output_port_lookup_v4_0_0 : used in encap_decap contrib-project
• lcam_output_port_lookup_v1_0_0 : used in reference_switch_lcam contrib-project

Limitations

All the reference projects work, without any issue, in hosts with 64GB of memory, with Vivado v2016.4.

If you have not registered to the NetFPGA-SUME beta program, you will need to do so to access the repository: Registration Form

You can find more information about NetFPGA-SUME code base in the NetFPGA-SUME wiki

More information about the release: Release-Notes

We invite everyone from the community to use and improve our repository, and hope to see a lot of projects contributed to the repository.

Kind Regards,

The NetFPGA team

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OSNT (Open-Source Network Tester) on SUME now available

Posted: 22 March 2017

Greetings Everyone,

We are pleased to announce the release of OSNT-SUME (available via www.osnt.org).

The initial OSNT-SUME project is a port of the NetFPGA-10G based OSNTsystem. We are currently planning a native implementation of OSNT-SUME thatwill be able to exploit all the SUME platform capabilities.

The OSNT-SUME repository follows the same criteria as the NetFPGA-SUME repository registration: http://netfpga.org/SUME-reg-form.html

Users that have access to the NetFPGA-SUME repo will have also the access to OSNT-SUME.

We invite everyone from the community to audit (and improve) our implementation as well as adapt it to their needs

More information can be found at: https://github.com/NetFPGA/OSNT-Public

NetFPGA developers are encouraged to use/contribute to OSNT-SUME repository:

https://github.com/NetFPGA/OSNT-SUME-live

More information about the Traffic Generator can be found at:

https://github.com/NetFPGA/OSNT-Public/wiki/OSNT-SUME-Generator

More information about the Traffic Monitor can be found at:

https://github.com/NetFPGA/OSNT-Public/wiki/OSNT-SUME-Monitor

More information about the software applications can be found at:

https://github.com/NetFPGA/OSNT-Public/wiki/OSNT-SUME-applications

Thanks, OSNT team

Meet NetFPGA

Posted: 22 March 2017

Greetings Everyone,

We have a fantastic set of events over the coming months for you to meet NetFPGA: meeting members of the NetFPGA platform team, and meeting people behind projects such as the P4 on NetFPGA and OSNT.

• Meet Salvator and Pietro in EPFL at DATE17 - UNIVERSITY BOOTH SESSION - Session 9 - 30/3/2017 - Thursday, 10:00-16:30 next week to see a demo of Emu
• Meet Andrew and Diana at PAM next week to hear about tools and benchmarks
• Attend the NetFPGA developers summit April 2017
• Attend the P4->NetFGA tutorial at P4 workshop (May 16th)
• For beginners, we have a NetFPGA summer camp in July, including the P4->NetFPGA tutorial - details to be announced shortly!
• Attend the P4->NetFPGA tutorial at SIGCOMM’17 at UCLA
• Along with many NetFPGA Systems talks such Noa’s talk at HUJI June’17 check out the Events page for up to date lists

I hope we will see you there,

Andrew and the NetFPGA team.

NetFPGA Design Challenge April 2017

Posted: 21 March 2017

Greetings Everyone,

We keenly encourage your participation in the NetFPGA Design Challenge April 2017

Prize updates:

With thanks to IMC we have a cash prize of £1,000

The winning projects and runner ups will be invited to present their work at the NetFPGA Developers Summit 2017. All challenge participants are keenly encouraged to attend the NetFPGA Developers Summit and are entitled to a reduced registration rate.

The design challenge prize pool is generously supported by IMC

More details can be found at: http://www.cl.cam.ac.uk/research/srg/netfpga/challenge2017

NetFPGA SUME Release 1.5.0

Posted: 13 December 2016

Greetings NetFPGA community,

We are pleased to announce today the next minor (1.5.0) of the NetFPGA-SUME code base.

The release includes:

Updates:

• nf_10ge_attachment_v1_0_0 : Fix the state machine conditions in tx and rx queue modules to revolve the interface stall issues. Fix the reset signal connection in tx and rx queue modules.

Bug Fix:

• reference_switch_lite: Fix the reset signal which caused negative slack in the reference_switch_lite bitfile
• axitools.py : Fix a typo, an undefined variable was crashing the script

If you have not registered to the NetFPGA-SUME beta program, you will need to do so to access the repository: Registration Form

You can find more information about NetFPGA-SUME code base in the NetFPGA-SUME wiki

More information about the release: Release-Notes

We invite everyone from the community to use and improve our repository, and hope to see a lot of projects contributed to the repository.

Kind Regards,

The NetFPGA team

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NetFPGA Development Challenge, April-2017

Posted: 16 November 2016

We are pleased to announce the 2017 NetFPGA Design challenge!

The NetFPGA 2017 contest has one design challenge. The design teams have 150 days to produce a working implementation employing any HW and SW design methodology and targeting the NetFPGA SUME platform. The contest begins on November 16th, 2016. The winners will be announced at the NetFPGA Developers summit (Thursday 20th - Friday 21st April, 2017, Cambridge UK)

Challenge: Lowest Latency Switch

Low latency devices are Low latency devices are being increasingly used across a large number of applications. Low latency solutions are few, and are rarely open source. The goal of this challenge is to provide a usable, high performance, open source alternative to use by universities and organizations who need the flexibility of open source.
The systems will be evaluated using OSNT, an Open Source Network Tester. Test benches will be available online prior to workshop day, for users to experiment and independently evaluate their design.
The competition is open to students of all levels (undergraduate and postgraduate), as well as to non students. There is no need to own a NetFPGA SUME platform to take part in the competition.
The competition is open to students of all levels (undergraduate and postgraduate), as well as to non students. There is no need to own a NetFPGA SUME platform to take part in the competition.
More details can be found at http://www.cl.cam.ac.uk/research/srg/netfpga/challenge2017

Good luck,

The NetFPGA team

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NetFPGA SUME Release 1.4.0

Posted: 4 October 2016

Greetings NetFPGA community,

We are pleased to announce today that the next minor update (1.4.0) of the NetFPGA-SUME code base.

The release includes:

Contributed Projects:

• Reference NIC-NFMAC10G: Implementation of the reference_nic based on the open-source 10GbE MAC
• delay_mb: A latency control gadget that provides latency variation and rate control
• reference_eu: Includes 3 designs written in C# and translated to Verilog, making use of the Kiwi Compiler

Contributed Cores:

• nfmac_10ge_interface_shared_v1_0_0: Open-source version of the Xilinx ten_gig_eth_mac
• nfmac_10ge_interface_v1_0_0: Open-source version of the Xilinx ten_gig_eth_mac
• delay_v1_0_0: FIFO-based module that control latency based on timestamps
• rate_limiter_v1_0_0: FIFO-based module for pacing of data out of the FIFO
• emu_output_port_lookup_v1_0_0: Output Port Lookup module that supports the reference_emu project

If you have not registered to the NetFPGA-SUME beta program, you will need to do so to access the repository: Registration Form

You can find more information about NetFPGA-SUME code base in the NetFPGA-SUME wiki

More information about the release: Release-Notes

We invite everyone from the community to use and improve our repository, and hope to see a lot of projects contributed to the repository.

Kind Regards,

The NetFPGA team

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NetFPGA SUME Release 1.3.0

Posted: 24 May 2016

Greetings NetFPGA community,

We are pleased to announce today the next minor release (1.3.0) of the NetFPGA-SUME code base.

The release includes:

Projects:

• Reference Router

Contributed Projects:

• Blue Switch

Cores:

• router_output_port_lookup_v1_0_0: Implementation of IPv4 – wiki page

Contributed Cores:

• nf_endianess_manager_v1_0_0: Data conversion between Little <-> Big endianess
• nf_sume_blueswitch_v1_0_0: Switch implementing multi-table, compliant with OpenFlow protocol – wiki page
• nf_sume_crossbar_v1_0_0: Part of the BlueSwitch Project – wiki page

Tools:

• Registers generation infrastructure: Updated version 2, support of indirect register access – wiki page

Patch:

• switch_output_port_v1_0_1:
  • Fix a typo in cam instantiation
  • Update the implementation run, to more aggressive timing closure mode
  • Add new CAM parameters (ADDR_TYPE, MATCH_ADDR_WIDTH)
• xparam2regdefines.py: Fix bug which produced multiple hashes

Xilinx cores:

• cam_v1_1_0/tcam_v1_1_0: Add new CAM parameters in the wrappers to support the ADDR_TYPE and MATCH_ADDR_WIDTH

If you have not registered to the NetFPGA-SUME beta program, you will need to do so to access the repository: Registration Form

You can find more information about NetFPGA-SUME code base in the NetFPGA-SUME wiki

More information about the release: Release-Notes

We invite everyone from the community to use and improve our repository, and hope to see a lot of projects contributed to the repository.

Kind Regards,

The NetFPGA team

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NetFPGA Newsletter February 2016

Posted: 1 February 2016

-=-=-

Hi and welcome to latest NetFPGA Newsletter

1. NetFPGA news
2. SUME release
3. NetFPGA Community - a solicitation

-=-=-

1. NetFPGA news

It is with great sadness the departure of two of the NetFPGA team in Cambridge.

Georgina Kalogeridou and Yury Audzevich have moved on from the University of Cambridge, each have been a huge contributor to the success of the NetFPGA project.

I hope they will involved in the NetFPGA project community.

We will sorely miss them both.

However, we do welcome Salvator Galea and Marcin Wojcik please each of them welcome as they contribute to the activities of the NetFPGA community.

-=-=- Want to be a contributor not just a consumer? email me -=-=-

NetFPGA SUME has had a new release

The new minor release_1.2.0 is up and running.

Updated also the news in the web page.

NetFPGA SUME v1.2.0

This release contains:

Projects:

• Acceptance Test: Added PCIe ibert test

Patch:

• NfSumeTest: Added a checkbox in the GUI of the acceptance_test to narrow down USB device listing

Bug Fix:

• Fixing an error in the Makefile of the acceptance_test project

-=-=- Want to advertise your NetFPGA course? Want to contribute to teaching material? Want to run a NetFPGA course? email me -=-=-

3. NetFPGA Community Event - a solicitation

We are considering a NetFPGA to be held on the 16th/17th April 2016 co-located with this year’s EuroSys conference in London.

If you are interested in this event or others like it please fill in the questionnaire at this URL

-=-=- Want to volunteer as a community-leader? email me. -=-=-

Best Wishes,

Andrew Moore.

NetFPGA SUME Release 1.2.0

Posted: 29 January 2016

Greetings NetFPGA community,

We are pleased to announce today the next minor release (1.2.0) of the NetFPGA-SUME code base.

The release includes:

Projects:

• Acceptance Test: Added PCIe ibert test

Patch:

• NfSumeTest: Added a checkbox in the GUI of the acceptance_test to narrow down USB listing

Bug fixes:

• Fixing a typo error in the Makefile of the acceptance_test project

If you have not registered to the NetFPGA-SUME beta program, you will need to do so to access the repository: Registration Form

You can find more information about NetFPGA-SUME code base in the NetFPGA-SUME wiki

More information about the release: Release-Notes

We invite everyone from the community to use and improve our repository, and hope to see a lot of projects contributed to the repository.

Kind Regards,

The NetFPGA team

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NetFPGA SUME release 1.1.0

Posted: 16 December 2015

Greetings NetFPGA community,

We are pleased to announce today the next minor release (1.1.0) of the NetFPGA-SUME code base.

The release includes:

Projects:

• reference_switch_lite, wiki page
• reference_switch, wiki page

Cores:

• cam_v1_0_0, wiki page
• tcam_v1_0_0, wiki page
• switch_output_port_lookup_v1_0_0

Bug fixes:

• Fixing a typo error in multiple cores

If you have not registered to the NetFPGA-SUME beta program, you will need to do so to access the repository: Registration Form

You can find more information about NetFPGA-SUME code base in the NetFPGA-SUME wiki

More information about the release: Release-Notes

We invite everyone from the community to use and improve our repository, and hope to see a lot of projects contributed to the repository.

Kind Regards,

The NetFPGA team

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NetFPGA SUME Release 1.0.0

Posted: 12 October 2015

Greetings NetFPGA community,

We are pleased to announce today the first release of the NetFPGA-SUME code base.

The release includes three reference projects:

• Acceptance test
• Reference NIC
• Reference switch

As usual our release also includes a unified test harness, device driver and all other components that make NetFPGA a platform.

NetFPGA-SUME is our first platform to use the Xilinx Vivado tool chain, and while the underlying infrastructure is very different, we believe that you will find the usage experience quite similar to our previous platforms, which should help you quickly and easily start using

If you have not registered to the NetFPGA-SUME beta program, you will need to do so to access the repository: Registration Form

You can find more information about NetFPGA-SUME code base in the NetFPGA-SUME wiki

More information about the release: Release-Notes

We invite everyone from the community to use and improve our repository, and hope to see a lot of projects contributed to the repository.

Kind Regards,

The NetFPGA team

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NetFPGA Newsletter June 2015

Posted: 15 June 2015

NetFPGA Newsletter June 2015

-=-=-

Hi and welcome to the latest slightly irregular NetFPGA Newsletter

1. Contributions
2. SUME news
3. SUME release
4. Tutorials and Workshops
5. NetFPGA plans

-=-=-

1. Contributions

We keenly encourage the NetFPGA community to contribute their projects for others - projects any boards (SUME, CML, 10G, 1G) are solicited.

-=-=- Have a project to contribute? email me -=-=-

2. SUME news

We have had some questions about changes to the NetFPGA SUME pricing and how best to order boards.

First of all, some brief background. NetFPGA SUME has a fantastic problem - it is an extremely popular board! This has led to its purchase (at the specially-discounted XUP price of 1,675 USD) by some people who are members of the XUP community but not contributors to the NetFPGA community. Xilinx, Digilent and the NetFPGA team have made the following changes to ensure that a sufficient supply of these specially-discounted boards is available to the members of the NetFPGA community.

The new price NetFPGA SUME for non-academic users is now 9,750 USD. The price for academic users who are not contributing to the NetFPGA community is 4,995 USD. The special price of 1,675 USD for contributors to the NetFPGA community is preserved. To ensure that there are sufficient boards at the specially-discounted for NetFPGA community members, we have the following guidance:

‘…

The specially discounted NetFPGA SUME boards are reserved for projects that contribute significantly to the open-source goals of the NetFPGA project.

To apply for the discounted rate, please submit a brief abstract of your Digilent using the link: https://netfpga.wufoo.com/forms/netfpga-special-pricing-request/

State clearly how your work contributes to the NetFPGA community. The requests will be evaluated by experts from both Xilinx and the NetFPGA team. Successful applicants will be advised by Digilent how to order their boards at the discounted prices.

…’

The intent of this arrangement is to prioritize access to the specially-discounted NetFPGA SUME boards for the active, contributing members of the NetFPGA community. All other academic groups will still be able to purchase the NetFPGA SUME boards at the higher, (but still heavily subsidized), price of 4,995 USD.

We hope that these arrangements will ensure a steady supply of NetFPGA SUME boards to the networking community.

For those that have had confusing messages from their local Digilent distributors, we encourage you to let Digilent at sales@digilentinc.com know the details as some distributors are operating with old information

-=-=-

3. SUME release

We are planning for SUME release 1.0 at the end of the week (26th of June).

This release will include

• An acceptance test for you to run to ensure your board is in good health.

The acceptance test was designed to test new boards in a standard operating mode, and it enables testing the major interfaces without special test fixtures.

• Following the acceptance test release, we will start to regularly release SUME reference projects, starting with the reference NIC.

This project is the first of our reference projects and as well as the corse to construct a reference NIC bitfile, it will include linux device drivers, and various support scripts. The reference NIC in this version uses the popular RIFFA DMA engine which is capable of PCI-e gen2 http://rffa.ucsd.edu

All the NetFPGA SUME projects are using Xilinx’s Vivado tool-chain and a tcl-based design flow.

• Simulation test environment

• Hardware test environment

For those wanting other reference projects - we have not forgotten you, we are simply running to catchup on this new board and once we have version 1.0 we will look to the future releases that will include

• Reference IPv4 Router
• Reference Ethernet Switch

and perhaps most exciting

• Reference Multi-table OpenFlow switch - compatible with 1.4

We are also working hard to have an open-source DMA engine that will perform as well as the hardware can offer - a labour of love - we will provide updates as we have them.

Look for announcements on the SUME mailing list.

-=-=- Want to be a contributor not just a consumer? email me -=-=-

4. Tutorials and Workshops

Here are upcoming tutorials and workshops currently in out calendar.

Courses are delivered in English unless otherwise noted.

Date: August 2-6, 2015
Location: Technion, Haifa, Israel
Type: One-week hands-on course
Hardware: NetFPGA-SUME
URL: http://www.cl.cam.ac.uk/research/srg/netos/netfpga/workshop/technion-august-2015/

Date: August 17, Morning session.
SIGCOMM 2015, London, Imperial College
Type: Half-day tutorial on Open Source Hardware including NetFPGA and OSNT
Hardware: NetFPGA-SUME
URL: http://conferences.sigcomm.org/sigcomm/2015/tutorial-ohwn.php

Date: August 31, Time TBA
FPL 2015, London, Imperial College
Type: Half-day NetFPGA tutorial
Hardware: NetFPGA_SUME
URL: TBA

If you wish to consider offering a course do get in contact.

-=-=- Want to advertise your NetFPGA course? Want to contribute teaching material? Want to run a NetFPGA course? email me -=-=-

5. NetFPGA Plans

I would like to give you some insight into our plans for NetFPGA going forward.

Our current status is this:

NetFPGA-SUME is our top-speed board and it will have the first bundle of software released for it in the coming week. Can you help us port and test interesting projects in the coming months?

NetFPGA-CML has replaced the NetFPGA-1G and is provided with the support of CML. This board supports users who want to build systems based on the reference projects with a limit to 1G Ethernet UTP cabling and 4 x 1Gb/s data rates. Additional facilities, including a CryptAuthentication chip and real-time clock are also part of the CML board.

NetFPGA-10G has been out venerable Virtex-5 workhorse and while projects will still be developed for this board at the end of 2015 we will look to move this board to join NetFGPGA-1G as being supported by the community. To make this happen we want community members to step forward who are willing to work alongside our development team, accepting patches as required and ensuring the 10G board questions get answered. Nothing arduous but this is a community board with community support. With volunteer help we expect to formally we expect to formally move the mailing list into the forums as we find these provide the best method for the community to support itself.

NetFPGA-1G is no longer available for purchase but continues to be supported by the community. If you want to volunteer to answer questions on NetFPGA-1G and to shepherd the forums - email me.

-=-=- Want to volunteer as a community-leader? email me -=-=-

Best wishes,
Andrew.
(temporary) editor of the NetFPGA newletter

-=-=- Want to edit the NetFPGA newsletter? email me. -=-=-

NetFPGA 1G CML Release 5.0.5

Posted: 26 May 2015

Greetings everyone,

We are happy to announce the next NetFPGA-1G-CML release (5.0.5).

Below you can find the release notes for 5.0.5:

1. projects/reference_nic_nf1_cml:
   The project was modified to support out-of-the-box configuration when it is installed in the on-board BPI during manufacturing.

2. projects/reference_nic_nf1_cml/sw/host/driver:
   The nf10 driver has been updated to support Linux Kernels 3.17.0 and later.

3. contrib-projects/nf1_cml_io_example:
   The project demonstrates the use of the onboard LEDs, buttons, SD card, PMODS and DDR memory using standard ISE/EDK IP modules.
   wiki: https://github.com/NetFPGA/NetFPGA-public/wiki/NetFPGA-1G-CML-IO-Example-Design

4. contrib-projects/nf1_cml_crypto_example:
   The project demonstrates how to access the on-board ATSHA204 CryptoAuthentication chip and on-board Real Time Clock. This project requires the ability to program the on-board PIC MCU. Please see the project README for more details
   wiki: https://github.com/NetFPGA/NetFPGA-public/wiki/NetFPGA-1G-CML-Crypto-Example

5. All reference projects in the ./projects directory that do not specifically target the NetFPGA-1G-CML PCB have been removed. This has been done to help reduce any confusion that may exist regarding which projects to use with which card

Thanks, –CML-Team & NetFPGA-Team

NetFPGA 10G Release 5.0.7

Posted: 8 April 2015

Greetings Everyone,

We are happy to announce the next NetFPGA-10G release (5.0.7)

Below you can find the release notes for 5.0.7:

1. nic_naas is a contributed project based on reference_nic project with a high performance DMA and driver.
   wiki: https://github.com/NetFPGA/NetFPGA-public/wiki/NiC-NaaS
   
   The above project includes the following new pcores:

   1. output queues with back pressure
      wiki: https://github.com/NetFPGA/NetFPGA-public/wiki/BRAM-Output-Queues-with-registers-and-back-pressure

   2. New DMA (dma v2.10a)
      wiki: https://github.com/NetFPGA/NetFPGA-public/wiki/DMA-v2.10
      and
      new device driver
      wiki: https://github.com/NetFPGA/NetFPGA-public/wiki/Linux-Device-Driver—NIC-NaaS

2. Updated test infrastructure to run tests of contrib-projects (nic_naas)

The NetFPGA development team along with the NetFPGA community is working diligently to extend and expand the 10G platform.

Thanks,

–NetFPGA-Team

OSNT Release 2.1.0

Posted: 28 February 2015

Greetings NetFPGA Community,

We are pleased to announce the next OSNT release (2.1.0).

Here are the release notes 2.1.0:

1. New 1G interface available with all the features provided for the 10G one:
   wiki: https://github.com/NetFPGA/OSNT-Public/wiki/1G-MAC-Interface-v1.20
   https://github.com/NetFPGA/OSNT-Public/wiki/DMA-v2.00

2. New OSNT_dualspeed project. This is OSNT with port0 and port1 working at 1G, while port2 and port3 working at 10G working at 10G.
   wiki: https://github.com/NetFPGA/OSNT-Public/wiki/OSNT_DUALSPEED
   https://github.com/NetFPGA/OSNT-Public/wiki/OSNT-Driver

The OSNT development team along with the OSNT community is working diligently to extend and expand the system.

Thanks,

OSNT Team

(www.osnt.org)

NetFPGA 10G Release 5.0.6

Posted: 13 January 2015

Greetings Everyone,

Wish you all a happy new year !!!

We are happy to announce the next NetFPGA-10G release (5.0.6).

This is a minor release and the release for 5.0.6 is below:

1. Patch for reference nic project to enable PCIe programming.

Thanks,

–NetFPGA-team

NetFPGA Newsletter December 2014

Posted: 22 December 2014

Hi and welcome to the slightly irregular NetFPGA Newsletter

It has been a busy year for NetFPGA in 2014 and this newsletter recaps a few exciting developments

1. SUME
2. Board refresh
3. Staffing changes and introductions
4. 2015 Expectations

1. SUME

NetFPGA SUME 1, described in detail in this article 2, is now available for order at the Digilent website 3.

While it might not be the ideal christmas stocking item; we are excited to see our new board getting into the hands of the user community. The Digilent site has the ordering details 3.

We will be setting up alpha and beta programmes as in previous years, and let you know when infrastructure is all ready to go; this will happen early in the new year.

2. Board refresh

Alongside the NetFPGA SUME which will server as our flagship project board, the answer to the often asked ‘will you be updating the NetFPGA-1G board’ the answer is a definite yes.

Together with Digilent and CML labs, a NetFPGA release for the CML board has been developed that provides access to ports of the existing (NetFPGA-10G) code base.

See the NetFPGA CML web pages for full details 4

If you want to help in some way please do get in touch.

3. Staff change and introductions

2014 saw the departure of long-standing NetFPGA staff Adam Covington, we are glad to hear he is enjoying life in the world beyond NetFPGA.

The team taking on the duties Adam has been doing consists of many people and as first in a series of introductions, I’d like to welcome Georgina Kalogeridou in the role of community manager. Georgina will be known to many of you as the author of the test and simulation frameworks for NetFPGA-10G. As part of this new community-manager role, Georgina has been responsible for the roll-out of the new website and alongside being NetFPGA web boss, she will take a more active role to ensure the mailing lists, online material, and forums work to support users across the entire NetFPGA ecosystem from the older 1G NetFPGA CML and our Flagship: NetFPGA SUME.

4. 2015 Expectations

We anticipate a busy 2015 for NetFPGA with tutorials for the new NetFPGA SUME in the planning, teaching materials in testing for the NetFPGA boards and a healthy community contributing to current and new projects.

I have plans that this newsletter become a regular item, I hope you won’t object and I promise a limit on number of emails to the netfpga announce list.

Wishing everyone a safe and happy holiday season and

best wishes for the new year,

Andrew.

(temporary) editor of the NetFPGA newsletter

NetFPGA 10G Release 5.0.5

Posted: 21 October 2014

Greetings Everyone,

We are happy to announce the next NetFPGA-10G release (5.0.5)

Below you can find the release notes for 5.0.5:

1. Added the Reference Router GUI interface:
   
   The Java GUI allows the user to change entries in the Routing Table and ARP cache as well as the router’s MAC and IP addresses. It also provides updates on counter values and graphs of throughput and much more.
   
   wiki: https://github.com/NetFPGA/NetFPGA-public/wiki/NetFPGA-10G-Reference-Router

2. Updated statistics for packets dropped counter at the interface:
   
   The NetFPGA development team along with the NetFPGA community is working diligently to extend and expand the 10G platform.

Thanks,

–NetFPGA-Team

Announcing NetFPGA SUME

Posted: 15 October 2014

We are excited to announce that new hardware will be joining the NetFPGA family of open-source networking platforms.

The new board, NetFPGA SUME, is an FPGA-based PCI Express board with I/O capabilities for 10 and 100 Gbps operation, an x8 Gen3 PCIe adapter card incorporating Xilinx’s Virtex-7 690T FPGA.

The peripheral subsystems adds to the four SFP+ transceivers with replaceable DDR3-SODIMM memories, QDRII+ memories, as well as presenting the 18 remaining transceivers into two expansion interfaces of eight and ten 13.1 Gbps (GTH) transceivers using an VITA-57 compliant FMC connector and an SAMTEC QTH-DP connector.

An article describing the card is to appear in the upcoming September/October issue of IEEE Micro Magazine. You can access the pre-print version of the paper in the following link.

At this stage, we want to register the interest in purchasing the board, so as to adapt the upcoming assembly’s quantities. If you are interested as an early adopter: joining the alpha programme, or to be kept up to date on the NetFPGA SUME, please fill in this form.

We hope you are as excited as we are to have this new addition to our growing family of open-source NetFPGA platforms, and we hope that you will be part of our exciting future.

The NetFPGA SUME team.

OSNT Release 2.0.0

Posted: 13 October 2014

Greetings NetFPGA Community,

We are pleased to announce the next OSNT release (2.0.0).

Here are the release notes for 2.0.0:

1. New DMA HW pcore now available:
   wiki: https://github.com/NetFPGA/OSNT-Public/wiki/DMA-v2.00

2. New driver now available:
   wiki: https://github.com/NetFPGA/OSNT-Public/wiki/OSNT-Driver

The OSNT development team along with the OSNT community is working diligently to extend and expand the system.

Thanks,

OSNT team (www.osnt.org)

NetFPGA 10G Release 5.0.4

Posted: 30 July 2014

Greetings Everyone,

We are happy to announce the next NetFPGA-10G release (5.0.4).

Here are the release notes for 5.0.4:

1. Project related information stored in the bitfile.

We have updated the nf10_identifier module to store information related to date and time the synthesis started, board id, release tag, project identification, project features and misc details. So that once the bitfile is loaded in the FPGA, the driver can parse these registers and give some useful information to the users.

Wikipage:
https://github.com/NetFPGA/NetFPGA-public/wiki/Project-related-information-in-bitfiles.

The NetFPGA development team along with the NetFPGA community is working diligently to extend and expand the 10G platform.

Thanks,

–NetFPGA-Team

NetFPGA publications list

Posted: 23 July 2014

Dear NetFPGA community members,

We are currently updating the contents of NetFPGA’s publication list, which can be seen through the following link https://netfpga.org/publications.html

Please contact me directly in case you have any publications involving the NetFPGA platform that are not mentioned in the list. This way we provide the most relevant project developments to the community.

Thanks,

Gianni Antichi
gianni.antichi@cl.cam.ac.uk

OSNT Release 1.5.0

Posted: 4 July 2014

Greetings NetFPGA Community,

We are pleased to announce the next OSNT release (1.5.0).

Here are the release notes for 1.5.0:

1. OSNT project is now able to generate packets with the transmission timestamp
   wiki: https://github.com/NetFPGA/OSNT-Public/wiki/10G-MAC-Interface-v1.20

2. Software code reorganization:
   wiki: https://github.com/NetFPGA/OSNT-Public/wiki/OSNT-Driver
   https://github.com/NetFPGA/OSNT-Public/wiki/OSNT-apps

The OSNT development team along with the OSNT community is working diligently to extend and expand the system.

Thanks,

OSNT team (www.osnt.org)

Open Source Network Tester Release 1.0.0

Posted: 6 May 2014

Greetings NetFPGA Community,

We are pleased to announce the release of OSNT (www.osnt.org).

The Open Source Network Tester (OSNT) based on the NetFPGA-10G platform, is a the world’s first open-source hardware traffic generator and capture system.

OSNT repository follows the same criteria as the NetFPGA-10G repository.

Users that have access to the NetFPGA-10G repo will also have access to OSNT.

We invite everyone from the community to audit (and improve) our implementation as well as adapt it to their needs.

More information can be found at https://github.com/NetFPGA/OSNT-Public NetFPGA developers are encouraged to use/contribute to OSNT repository.

More information about the Traffic Generator can be found at https://github.com/NetFPGA/OSNT-Public/wiki/OSNT-Traffic-Generator

More information about the Traffic Monitor can be found at https://github.com/NetFPGA/OSNT-Public/wiki/OSNT-Traffic-Monitor

Thanks,

OSNT team

University of Wisconsin, Madison

Presenter: Andrew Moore

Posted: 2 April 2013

Location: Room 4130, 1210 W. Dayton St, Madison, WI 53706-1685

Goal: One hour 10G Introductory

NetFPGA 10G Public Beta

Posted: 15 March 2012

We are happy to announce NetFPGA 10G Public Beta. This release is public, meaning open to everyone. There will be limited support while the programme is in Beta.

Register for access here.

Project webpage: http://www.netfpga.org

The NetFPGA-10G features include:

• Xilinx Virtex-5 XC5VTX240
• Four SFP+ interface (using 16 RocketIO GTX transceivers and 4 PHY devices)
• Support for both 10Gbps and 1Gbps modes
• X8 PCI express Gen 2 (5Gbps/lane)
• Twenty Configurable GTX Serial transceivers (available through two high-speed Samtec connectors)
• Three x36 QDR II (CY7C1515JV18) - Four x32 RLDRAM II (MT49H16M36HT-25)

NetFPGA Summer Camp 2011 Registration Online

Posted: 2 May 2011

The registration site for the 2011 NetFPGA Summer Camp at Stanford University is now on-line. Summer Camp will be held August 1st-5th.

Register before June 15th for only $250. After June 15th the price will be $350.

As noted at the end of the event homepage, it is now possible to register for the event or apply for a scholarship.

The link to register on-line is here.

A limited number of scholarships are also available for students or instructors from schools unable to cover registration and hotel expenses. Award of the scholarships will be based on both merit and need. The application form for the scholarship is available on-line.

NetFPGA Summer Camp 2011

Posted: 7 March 2011

Mark your calendars. We are planning another NetFPGA Summer Camp this year. The camp will be held at Stanford, August 1st-5th.

More information will be sent as the webpage and registration is set up.

NetFPGA 2.2.0 Released

Posted: 21 January 2011

NetFPGA 2.2.0 is released.

Below is a brief description of improvements. Visit the release page to see the entire change log and bug fixes.

Improvements:

• Gigabit MAC/Tri-mode Ethernet MAC:
  • allow TEMAC to be substituted for Gigabit MAC
  • Switch all reference projects to Gigabit MAC
• Xen:
  • Driver and tools will now work in a Xen virtualization environment. (See the website for documentation.)
• crypto_nic:
  • tests updated to reflect library location updates
• Wireshark:
  • Include plugins for:
    • PWOSPF
    • event_capture
  • Note: These currently do not compile without work from the user
• Driver:
  • add support for /sys/class/net under Linux 2.6+
• fetch_mem_models:
  • included a script for fetching the memory models for simulation
• build system:
  • UCF files provided by modules will be merged.

NetFPGA Summer Camp

Posted: 2 July 2010

NetFPGA Summer Camp at Stanford University will be August 9th-13th 2010. Registration deadline: June 15th

Register at: Registration Site A limited number of Scholarships are available for students or instructors from schools unable to cover registration and hotel expenses. To apply for a scholarship, please fill in the application.

NetFPGA Kentucky Tutorial

Posted: 29 March 2010

We are pleased to announce an upcoming NetFPGA tutorial in Lexington, KY on March 21, 2010.

During the tutorial, we will use the NetFPGA to determine the amount of memory needed to buffer TCP/IP streaming through the Gigabit/second router. Hardware circuits within the NetFPGA will be implemented to measure and plot the occupancy of buffers. Circuits will be downloaded into reconfigurable hardware and tested with live, streaming Internet video traffic.

Attendees will utilize a Linux-based PC equipped with NetFPGA hardware. A basic understanding of Ethernet switching and network routing is expected. Past experience with Verilog is useful but not required.

Details about this event and registration information are posted on-line.

NetFPGA Design Contest 2010

Posted: 29 March 2010

The Stanford NetFPGA team is pleased to announce the 2010 NetFPGA Design Contest!

The NetFPGA is an open platform developed at Stanford University. The NetFPGA platform enables researchers and instructors to build high-speed, hardware-accelerated networking systems. The platform can be used by researchers to prototyped advanced services for next-generation networks. By using Field Programmable Gateway Arrays (FPGAs), the NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained. The contest is split into two challenges. Teams can participate in either or both challenges. The design teams have 120 days to produce a working implementation employing any HW and SW design methodology and targeting the NetFPGA development platform. The contest begings Feb 9th, 2010.

Challenge 1: The Best Network Tester/Packet Capture system There are a small number of very expensive packet generator and capture systems on the market, used for testing networks and network equipment. The goal of this design is to provide a usable, powerful and open-source alternative for use by universities and organizations unable to afford such expensive equipment.

Challenge 2: The Best Overall Network Design System The goal is to design and implement a novel design on the NetFPGA system. Use your imagination to devise a new use case for the NetFPGA. We are looking for solutions utilizing the NetFPGA cards that perform significant networking functionality. The 1st place team will receive: $1,000 cash award, two NetFPGA-1G cards (or one NetFPGA-10G cards when they become available), and the right to choose a school to receive 5 new NetFPGA-1G cards. Up to two team members will receive an expenses-paid trip (flight, hotel and registration) to come and present your design at a NetFPGA Developers Conference. The 2nd place team will receive $600 cash award. The 3rd place team will receive $400 cash award.

NetFPGA Demo wins 2nd place at SIGCOMM

Posted: 21 August 2008

Congratulations to Neda and the rest of the NetFPGA team for the successful demonstration of the NetFPGA at the SIGCOMM 2008 conference. The demonstration was second only to the OpenFlow demo, which was awarded as the best demonstration at the conference. The NetFPGA demo, Programmable Routers in Real Networks, modulated the size of a NetFPGA routers packet buffer deployed within the Internet2 to study the effect of TCP throughput. Live data from the experiment was charted on a Java GUI to confirm that the model predicteding the buffer size of RTT*C/Sqrt(N) provides an upper bound on the buffer size needed to obtain full throughput in the network.