NetFPGA Summer Camp 2010

Build an Internet routers and learn about clean-slate switches at a 5-day summer camp held at Stanford University

Presented by: the Stanford NetFPGA Group

Open to: Academics teaching with the NetFPGA, and researchers (postdoc or graduate-student) interested in develping new hardware-accelerated network applications

Date: Monday, August 9 - Friday, August 13, 2010

Time: 9am - 5pm. Evening events will be announced here

Location: The Stanford University campus located between San Francisco and San Jose in the heart of the Silicon Valley


This week-long summercamp extends the material presented at the shorter workshop events.

A photo from the summer camp


Day 1 (Monday, Aug. 9)

  • Welcome and introductions
  • Day 1
    • Background
      • Basics of an IP router
      • The NetFPGA hardware
      • How people use the NetFPGA
      • Why people use NetFPGA
    • The Stanford Base Reference Router
      • Inside the NetFPGA hardware
      • Introduction to FPGAs and Verilog
    • The Enhanced Reference Router
      • Buffer sizing requirements in a router
      • Observering and controlling the queue size
    • Life of a packet through the NetFPGA
      • Data and control planes
      • Interface to software: Exceptions and Host I/O
    • Demonstration of the NetFPGA
      • Address Lookup
      • PW-OSPF
      • Java-based Graphical User Interface (GUI)
      • Demonstration of High Definition (HD) video streaming
    • Slides: Will be available here

Day 2 (Tuesday, Aug. 10)

  • Module Development and Testing
    • Running Model Sim with the NetFPGA TestBench
      • Compile, simulate, view waveforms
      • Example: Simply Encryption on a packet payload
      • Scrambling the payload with XOR using a key from a register
    • Regression testing to verify hardware functionality
      • Synthesize and run the hardware
      • Verify value: 0xFFFFFFFF (would invert every bit of every byte of payload)
      • Verify value: 0xFF00FF00 (would invert every other byte of payload)
      • Verify value: 0x55555555 (would invert every other bit of payload)
    • Slides: Will be available here
  • Group discussion
    • Projects ideas
    • Scope of work that can be accomplished in 2-3 days
  • Team up for Projects
    • Project leaders will describe projects
    • Group will provide feedback on the scope
    • Be sure to have one hardware designer per team
  • Example Hardware Design
    • Background and review of block diagrams
    • Show design running on nf-test machines
    • Discuss relevant Verilog Code

Day 3 (Wednesday, Aug. 11)

  • Work on Projects, examples from Summerschool 2010
    • 802.1q VLANs
    • Hardware-Accelerated Mathematics Library for NetFPGA
    • MACinMAC
    • Heavy Hitter Identification using Multistage filters
    • Layer 2 Load Balancing
    • Pattern Matching/Mini-IDS
    • TCP Traffic Analysis for Passive End-to-End Bandwidth Measurement
    • Assessment of Prototyping an ADFX Policy Switch Leveraging NetFPGA, Ethane, and OpenFlow Switch
    • ntop on NetFPGA
    • Universal Hash Function
  • NetFPGA group available for Questions and Answers
  • Dinner: Pizza in the Fijitsu Lounge, Gates Building, 6pm

Day 4 (Thursday, Aug. 12)

  • Complete Projects
  • 10-minute project presentations.
  • Live demonstrations
  • Award prizes to winning projects

Day 5 (Friday, Aug. 13)

  • NetFPGA Developers Conference
  • Dinner: MacArthur Park 7pm

Saturday, Aug. 14

  • Checkout of Stanford Guest House

Background Reading

To Attend this Event

  • Mark your calendar with the dates of the event
    • Please plan to arrive Sunday night, August 8
    • Please plan to stay through Saturday morning, August 14
    • Registration fee covers shared meals (all breakfasts, lunches, and most dinners)
      • Registration Fee: $450
      • Register: Registration Site
      • Registration Deadline: June 15th
    • A limited number of scholarships are available for students or instructions from schools unable to cover registration and hotel expenses. Scholarship applicants do not need to register through the registration website
      • Award of the scholarships will be based on both merit and need:
      • Please provide one paragraph about that describes your relevant technical background in networking and/or hardware design
      • Please provide another paragraph that explains why you or your host institution needs financial help.
      • Scholarship Application:
  • Travel Information
    • Direct flights are available to most parts of the country through SFO or SJC
    • CalTrain offers fast transportation between the airports and Palo Alto
    • The Marguerite Shuttle offers rides between the train station, hotel and campus. No car rental is needed.
  • Book accommodations at the Stanford Guest House.
    • There are a block of rooms reserved for the NetFPGA event
    • These rooms are only guaranteed to be available until 06/29/2010
    • To reserve rooms call: (650) 926-2800 with the reservation code 'NetFPGA'
    • Single rooms are $109/night
    • Double rooms are $139/night
    • Shuttle services available to campus